公开(公告)号：US09324942B1

公开(公告)日：2016-04-26

申请号：US13756498

申请日：2013-01-31

申请人： Crossbar, Inc.

发明人： Hagop Nazarian ,  Tanmay Kumar ,  Sung Hyun Jo

IPC分类号： H01L45/00

CPC分类号： H01L45/085 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/148

摘要： Providing for a solid state memory cell having a resistive switching memory cell with rectifier characteristics is described herein. By way of example, the solid state memory cell can have one or more layers creating a resistive switching device capable of achieving and maintaining different electrical resistances in response to different voltages applied to the solid state memory cell. Moreover, the solid state memory cell can comprise two or more layers creating a solid state diode device electrically in series with the resistive switching device. The solid state diode device can be configured to permit very low current through the solid state memory cell at voltages less than a breakdown voltage or reverse breakdown voltage. The rectifier characteristics can mitigate sneak path currents in a crossbar memory array, or similar array, facilitating greater sensing margin, reduced likelihood of memory errors, greater die concentration, fast switching times, and other benefits.

摘要翻译： 本文描述了具有具有整流器特性的电阻式开关存储单元的固态存储单元。 作为示例，固态存储单元可以具有一个或多个层，其产生能够响应于施加到固态存储单元的不同电压来实现和维持不同电阻的电阻式开关器件。 此外，固态存储单元可以包括两个或更多个层，产生与电阻式开关器件串联电连接的固态二极管器件。 固态二极管器件可被配置为允许在小于击穿电压或反向击穿电压的电压下通过固态存储单元的非常低的电流。 整流器特性可以减轻交叉开关存储器阵列或类似阵列中的潜行路径电流，有利于更大的感测裕度，降低存储器错误的可能性，更大的管芯集中度，更快的切换时间和其他优点。

公开(公告)号：US09312483B2

公开(公告)日：2016-04-12

申请号：US13625817

申请日：2012-09-24

申请人： Crossbar, Inc.

发明人： Steven Patrick Maxwell

IPC分类号： H01L29/02 ,  H01L45/00

CPC分类号： H01L45/148 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1616 ,  H01L45/1675

摘要： A method of forming a resistive switching device includes forming a wiring structure over a first dielectric and substrate, forming a junction layer over the wiring structure, forming a resistive switching layer over the junction layer, forming an active metal over the resistive switching layer, forming a tungsten layer over the active metal, forming a barrier layer over the tungsten, depositing a mask over the barrier layer, etching the barrier layer to form a hard mask, etching the junction layer, the resistive switching layer, the active metal layer, and the adhesion layer using the hard mask to form a stack of material, while the adhesion layer maintains adhesion between the barrier layer and the active metal and while side walls of the stack of material have reduced contaminants and have reduced gap regions between the barrier layer and the resistive switching layer.

摘要翻译： 形成电阻性开关器件的方法包括在第一电介质和衬底上形成布线结构，在布线结构之上形成结层，在结层上形成电阻开关层，在电阻开关层上形成有源金属，形成 在所述活性金属上形成钨层，在所述钨上形成阻挡层，在所述阻挡层上沉积掩模，蚀刻所述阻挡层以形成硬掩模，蚀刻所述接合层，所述电阻开关层，所述活性金属层和 使用硬掩模的粘合层形成一堆材料，同时粘合层保持阻挡层和活性金属之间的粘合性，并且当堆叠材料的侧壁具有减少的污染物并且在阻挡层和 电阻式开关层。

公开(公告)号：US09252191B2

公开(公告)日：2016-02-02

申请号：US13189401

申请日：2011-07-22

申请人： Mark Harold Clark ,  Scott Brad Herner

发明人： Mark Harold Clark ,  Scott Brad Herner

IPC分类号： H01L21/02 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2463 ,  H01L21/02532 ,  H01L21/0262 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1675

摘要： A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.

摘要翻译： 一种形成非易失性存储器件的方法包括提供具有表面的衬底，沉积覆盖在表面上的电介质，形成覆盖电介质的第一布线结构，沉积覆盖第一布线结构的硅材料，硅层的厚度 小于约100埃，使用硅层作为种子层，以大约400至大约490摄氏度的温度沉积硅锗材料，其中硅锗材料基本上没有空隙并具有多晶特性 沉积覆盖硅锗材料的电阻开关材料（例如非晶硅材料），沉积覆盖电阻材料的导电材料，以及形成覆盖导电材料的第二布线结构。

公开(公告)号：US09166163B2

公开(公告)日：2015-10-20

申请号：US14027045

申请日：2013-09-13

申请人： Crossbar, Inc.

发明人： Harry Yue Gee ,  Mark Harold Clark ,  Steven Patrick Maxwell ,  Sung Hyun Jo ,  Natividad Vasquez, Jr.

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/1633

摘要： Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

摘要翻译： 本文描述了提供双端存储器件的制造，构造和/或组装。 双端存储器件可以包括具有硅轴承层，界面层和活性金属层的有源区。 可以创建界面层，其包括可以是具有聚集化学式SiO x的多个硅和/或氧化硅层的组合的非重质亚氧化物，其中X可以是大于零且小于2的非整数 亚氧化物可以以各种方式产生，包括与生长亚氧化物，沉积亚氧化物或将现有薄膜转化为亚氧化物相关的各种技术。

公开(公告)号：US09129887B2

公开(公告)日：2015-09-08

申请号：US13739283

申请日：2013-01-11

申请人： Crossbar, Inc.

发明人： Sung Hyun Jo

IPC分类号： H01L21/00 ,  H01L49/02 ,  G11C11/22 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L28/20 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2213/33 ,  G11C2213/56 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/1675

摘要： A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

摘要翻译： 非易失性电阻式开关存储器件。 该装置包括第一电极，第二电极，与第二电极的金属区域直接接触的开关材料，以及设置在第二电极和开关材料之间的电阻材料。 电阻材料具有与开关器件的导通状态电阻基本相同的欧姆特性和电阻。 电阻材料允许在施加电压脉冲时开关材料的电阻变化而没有时间延迟并且在电压脉冲之后没有反向偏置。 第一电压脉冲导致编程电流从第二电极流向第一电极。 电阻材料进一步使编程电流不大于预定值。

公开(公告)号：US09047939B2

公开(公告)日：2015-06-02

申请号：US14166691

申请日：2014-01-28

申请人： Crossbar, Inc.

发明人： Harry Kuo ,  Hagop Nazarian

IPC分类号： G11C5/06 ,  G11C13/00 ,  G11C7/18

CPC分类号： G11C13/0004 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C2207/005 ,  G11C2213/15 ,  G11C2213/78

摘要： A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

摘要翻译： 非易失性存储器件包括存储单元阵列，每个存储器单元具有电阻存储器单元和本地字线。 每个存储单元具有第一端和第二端，第二端耦合到相应存储单元的本地字线。 提供位线，每一个都连接到每个电阻存储器单元的第一端。 提供了多个选择晶体管，每个选择晶体管与一个存储器单元相关联并且具有耦合到相关联的存储器单元的本地字线的漏极端子。 提供第一和第二全局字线，每个字线耦合到至少一个选择晶体管的控制端。 提供第一和第二源极线，每个耦合到至少一个选择晶体管的源极端子。 存储器件被配置为在读取操作中同时读出一个选择的存储器单元中的所有电阻存储器单元。

公开(公告)号：US08982647B2

公开(公告)日：2015-03-17

申请号：US13676943

申请日：2012-11-14

申请人： Crossbar, Inc.

发明人： Hagop Nazarian ,  Sang Nguyen

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C11/02 ,  G11C11/22 ,  G11C11/34 ,  G11C5/12 ,  G11C11/16 ,  G11C7/06 ,  G11C13/00

CPC分类号： G11C7/12 ,  G11C5/12 ,  G11C7/062 ,  G11C11/02 ,  G11C11/1673 ,  G11C11/2297 ,  G11C11/34 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/78 ,  Y10T29/41

摘要： Providing for a two-terminal memory architecture that can mitigate sneak path current in conjunction with memory operations is described herein. By way of example, a voltage mimicking mechanism can be employed to dynamically drive un-selected bitlines of the memory architecture at a voltage observed by a selected bitline. According to these aspects, changes observed by the selected bitline can be applied to the un-selected bitlines as well. This can help reduce or avoid voltage differences between the selected bitline and the un-selected bitlines, thereby reducing or avoiding sneak path currents between respective bitlines of the memory architecture. Additionally, an input/output based configuration is provided to facilitate reduced sneak path current according to additional aspects of the subject disclosure.

摘要翻译： 本文描述了提供可以减轻潜行路径电流与存储器操作相结合的两终端存储器架构。 作为示例，可以采用电压模拟机构来以所选择的位线观察到的电压来动态地驱动存储器架构的未选定位线。 根据这些方面，所选位线观察到的变化也可以应用于未选定的位线。 这可以帮助减少或避免所选择的位线与未选择的位线之间的电压差，从而减少或避免存储架构的相应位线之间的潜行路径电流。 另外，提供了基于输入/输出的配置，以根据本发明的另外的方面来促进减少的潜行路径电流。

公开(公告)号：US08975609B2

公开(公告)日：2015-03-10

申请号：US13862353

申请日：2013-04-12

申请人： Crossbar, Inc.

发明人： Harry Gee ,  Sung Hyun Jo ,  Hagop Nazarian ,  Scott Brad Herner

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L21/4763 ,  G11C13/00 ,  H01L27/24

CPC分类号： H01L45/1683 ,  G11C13/0007 ,  G11C2213/71 ,  H01L21/4763 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16

摘要： A method of forming a non-volatile memory device. A substrate is provided and a first dielectric material forms overlying the substrate. A first polysilicon material is deposited overlying the first dielectric material. A second dielectric material is deposited overlying the first polysilicon material. A second polysilicon material is deposited overlying the second dielectric material. A third dielectric material is formed overlying the second polysilicon material. The third dielectric material, the second polysilicon material, the second dielectric material, and the first polysilicon material is subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material, a third wordline and associated with a third switching device, and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and overlies the amorphous silicon material and connected to a common bitline.

摘要翻译： 一种形成非易失性存储器件的方法。 提供衬底并且形成覆盖衬底的第一介电材料。 第一多晶硅材料沉积在第一介电材料上。 沉积在第一多晶硅材料上的第二介电材料。 第二多晶硅材料沉积在第二介电材料上。 形成覆盖第二多晶硅材料的第三介电材料。 对第三介电材料，第二多晶硅材料，第二介电材料和第一多晶硅材料进行第一图案和蚀刻工艺以形成与第一开关器件相关联的第一字线和与第二开关器件相关联的第二字线 来自第一多晶硅材料的第三字线和与第三开关器件相关联的第三字线以及与第四开关器件相关联的第四字线从第二多晶硅材料。 形成通孔开口以将第一字线与第二字线分开，并将第三字线与第四字线分开。 将非晶硅开关材料顺应地沉积在通孔开口上方。 金属材料填充通孔开口并覆盖非晶硅材料并连接到公共位线。

公开(公告)号：US08952349B2

公开(公告)日：2015-02-10

申请号：US13960735

申请日：2013-08-06

申请人： Crossbar, Inc.

发明人： Wei Lu ,  Sung Hyun Jo

IPC分类号： H01L45/00 ,  H01L21/06 ,  G11C11/00 ,  H01L27/24 ,  H01L27/10

CPC分类号： H01L27/2409 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/148

摘要： A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

摘要翻译： 开关装置包括：基板; 形成在所述基板上的第一电极; 形成在所述第一电极上的第二电极; 布置在第一和第二电极之间的开关介质; 以及设置在第一和第二电极之间并且与第一电极和开关介质串联电耦合的非线性元件。 非线性元件被配置为在施加大于阈值的电压时从第一电阻状态改变到第二电阻状态。

公开(公告)号：US08912523B2

公开(公告)日：2014-12-16

申请号：US13870919

申请日：2013-04-25

申请人： Crossbar, Inc.

发明人： Sung Hyun Jo

IPC分类号： H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L45/00

CPC分类号： H01L45/12 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/148

摘要： A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.

摘要翻译： 非易失性存储器件结构。 器件结构包括第一电极，第二电极，包括覆盖在第一电极上的非晶硅材料的电阻开关材料，以及设置在第二电极和电阻器之间的厚度范围为5nm至10nm的介电材料的厚度 开关层。 介电材料的厚度被配置为在向第二电极施加电铸电压时在区域中电击穿。 电击穿允许在电阻开关材料的一部分中形成具有小于约10nm×10nm的尺寸的金属区域。