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公开(公告)号：US11710511B2
公开(公告)日：2023-07-25
申请号：US17501411
申请日：2021-10-14
摘要： A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.
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公开(公告)号：US20230231407A1
公开(公告)日：2023-07-20
申请号：US18146708
申请日：2022-12-27
发明人： Masaki HOGARI , Masaru MIYAKE , Yasuo USUDA , Youhei KENGOYAMA , Tetsuo MIYAUCHI
CPC分类号： H02J7/007194 , H02J7/0047 , H01M10/425 , H01M10/486 , H01M10/443
摘要： Provided is a semiconductor device capable of stably estimating an internal temperature of a battery. A semiconductor device coupled to a battery calculates entropy heat of the battery at a predetermined time by using a charging current of the battery and an internal temperature of the battery at a time before a predetermined time, calculates a heat generation amount of the battery from the charging current of the battery, calculates a heat radiation amount of the battery based on a temperature difference between the internal temperature at the time before the predetermined time and a surface temperature of the battery, and estimates an internal temperature of the battery at the predetermined time by using the entropy heat, the heat generation amount and the heat radiation amount.
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公开(公告)号：US20230231011A1
公开(公告)日：2023-07-20
申请号：US18189463
申请日：2023-03-24
发明人： Satoru Tokuda
IPC分类号： H01L29/06 , H01L29/66 , H01L29/423
CPC分类号： H01L29/0634 , H01L29/66734 , H01L29/4238 , H01L29/4236
摘要： A semiconductor device that achieves both miniaturization and high breakdown voltage is disclosed. The semiconductor device has a gate electrode G1 formed in a trench TR extending in Y direction and a plurality of column regions PC including column regions PC1 to PC3 formed in a drift region ND. The column regions PC1, PC2 and PC3 are provided in a staggered manner to sandwich the trench TR. An angle θ1 formed by a line connecting the centers of the column regions PC1 and PC2 and a line connecting the centers of the column regions PC1 and PC3 is 60 degrees or more and 90 degrees or less.
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公开(公告)号：US11705344B2
公开(公告)日：2023-07-18
申请号：US17405550
申请日：2021-08-18
CPC分类号： H01L21/565 , H01L21/02041 , H01L2924/181
摘要： A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.
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公开(公告)号：US20230197827A1
公开(公告)日：2023-06-22
申请号：US18052382
申请日：2022-11-03
发明人： Zhichao LIN , Koji OGATA , Yukio TAKAHASHI , Tomohiro IMAI , Tetsuya YOSHIDA
IPC分类号： H01L29/66 , H01L29/739 , H01L29/06 , H01L29/08 , H01L21/28 , H01L21/265
CPC分类号： H01L29/66348 , H01L29/7397 , H01L29/0638 , H01L29/0834 , H01L21/28185 , H01L21/28211 , H01L21/26513
摘要： A gate electrode is formed inside a trench via a gate insulating film. The gate insulating film formed on a semiconductor substrate is removed. An insulating film is formed on the semiconductor substrate. A p-type base region is formed in the semiconductor substrate. An n-type emitter region is formed in the base region. Hydrogen annealing process is performed to the semiconductor substrate. A boundary between the base region and the emitter region is located at a position deeper than the insulating film formed between a side surface of the trench and the gate insulating film.
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公开(公告)号：US20230195523A1
公开(公告)日：2023-06-22
申请号：US18055598
申请日：2022-11-15
发明人： Kenta KANDA
IPC分类号： G06F9/50
CPC分类号： G06F9/5027
摘要： An exclusive control processing that is complex is eliminated on tasks executed in processors. A semiconductor device includes: a memory that stores task management information and running group management information; a first PE and a second PE; and a first shared resource and a second shared resource, and the first PE or the second PE is configured to refer to the running group management information and specify a group of tasks executable in the first PE or the second PE as an executable group, and to refer to the task management information and determine a task associated with group identification information of the specified executable group as a task to be executed next in the first PE or the second PE.
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公开(公告)号：US20230187275A1
公开(公告)日：2023-06-15
申请号：US18164153
申请日：2023-02-03
发明人： Katsuhiko HOTTA , Kyoko SASAHARA
IPC分类号： H01L21/768 , H01L21/8238 , H01L23/525 , H01L23/532 , H01L23/00 , H01L23/522 , H01L23/528 , H01L21/8234
CPC分类号： H01L21/76832 , H01L21/76808 , H01L21/76811 , H01L21/76834 , H01L21/76841 , H01L21/76895 , H01L21/823475 , H01L21/823871 , H01L23/528 , H01L23/5226 , H01L23/5258 , H01L23/5283 , H01L23/5329 , H01L23/53209 , H01L23/53238 , H01L23/53295 , H01L24/11 , H01L2224/13099 , H01L2924/00 , H01L2924/014 , H01L2924/14 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/04941 , H01L2924/04953 , H01L2924/12042 , H01L2924/19043 , H01L2924/30105
摘要： For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
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公开(公告)号：US11677412B2
公开(公告)日：2023-06-13
申请号：US17529885
申请日：2021-11-18
发明人： Tomohiko Ebata
CPC分类号： H03M1/46 , H03M1/1245
摘要： A semiconductor device performs sequential comparison of an analog input signal and a reference voltage to digitally convert the analog input signal. The semiconductor device includes an upper DAC generating a high-voltage region of the reference voltage based on a predetermined code, a lower DAC generating a low-voltage region of the reference voltage based on the code, and an injection DAC having the same configuration as that of the lower DAC and adjusting the low-voltage region of the reference voltage.
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公开(公告)号：US11675404B2
公开(公告)日：2023-06-13
申请号：US17319880
申请日：2021-05-13
发明人： Ryo Mori , Kazuki Fukuoka , Kenichi Shimada
摘要： A semiconductor device includes: a plurality of cores configured to receive power from a power supply; a plurality of power switch circuits provided for each core and configured to control the power supplied to the corresponding cores; a compare circuit configured to receive power from the power supply and compare output data of the plurality of cores; and a core voltage monitor circuit configured to monitor a voltage of a node that connects the power supply and the compare circuit.
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公开(公告)号：US20230176883A1
公开(公告)日：2023-06-08
申请号：US17938475
申请日：2022-10-06
IPC分类号： G06F9/455 , G06F9/4401
CPC分类号： G06F9/45541 , G06F9/4406
摘要： According to one embodiment, a semiconductor device restricts an OS capable of using a functional block by an OS identifier written in an attribute register for restricting an accessible OS, and creates operation setting values of a first input unit, a second input unit, and a screen synthesis unit per OS to describe them in a setting value list stored in a shared memory, and each of the first input unit, second input unit, and screen synthesis unit has a mask circuit that refers to the OS identifier of the attribute register and in which write of the operation setting values into the setting register group of an own block is hampered, the operation setting values being described in the setting value list created by an OS other than the OS having a use authority for the own block.
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