公开(公告)号：US20240249996A1

公开(公告)日：2024-07-25

申请号：US18099949

申请日：2023-01-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael FLYNN ,  Otto JOE

IPC: H01L23/42 ,  H01L21/48 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/42 ,  H01L21/4817 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311

Abstract: A method and apparatus are provided which manages the movement of thermal interface material (TIM) squeezed out from between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes an IC die mounted on a substrate and covered by a lid. A bottom surface of the lid has a die overlapped region facing a top surface of the IC die. The bottom surface of the lid has a first gutter formed therein. An outer sidewall of the first gutter is formed outward of the first die overlapped region as to receive TIM squeezed out from between a lid and an IC die.

公开(公告)号：US12045182B1

公开(公告)日：2024-07-23

申请号：US18298587

申请日：2023-04-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Christopher Morton ,  Pravesh Gupta ,  Bryan P Broussard ,  Li Ou

IPC: G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F13/26 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/4812 ,  G06F9/4818 ,  G06F9/4831 ,  G06F13/26 ,  G06F13/4221

Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

公开(公告)号：US12033721B2

公开(公告)日：2024-07-09

申请号：US17359446

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

公开(公告)号：US12033238B2

公开(公告)日：2024-07-09

申请号：US17030852

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Brian D. Emberling ,  Joseph Lee Greathouse ,  Anthony Thomas Gutierrez

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for implementing register compaction with early release are disclosed. A processor includes at least a command processor, a plurality of compute units, a plurality of registers, and a control unit. Registers are statically allocated to wavefronts by the control unit when wavefronts are launched by the command processor on the compute units. In response to determining that a first set of registers, previously allocated to a first wavefront, are no longer needed, the first wavefront executes an instruction to release the first set of registers. The control unit detects the executed instruction and releases the first set of registers to the available pool of registers to potentially be used by other wavefronts. Then, the control unit can allocate the first set of registers to a second wavefront for use by threads of the second wavefront while the first wavefront is still active.

公开(公告)号：US12033035B2

公开(公告)日：2024-07-09

申请号：US16560954

申请日：2019-09-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Jehandad Khan ,  Daniel Isamu Lowell

IPC: G06N20/00 ,  G06F11/34 ,  G06N3/02

CPC classification number: G06N20/00 ,  G06F11/3409 ,  G06N3/02

Abstract: A processing device, which improves processing performance, is provided which comprises memory configured to store data and a processor, in communication with the memory. The processor is configured to receive tuning parameters, each having a numeric value, for executing a portion of a program on an identified hardware device and convert the numeric values of the tuning parameters to words. The processor is also configured to predict, using one or more machine language learning algorithms, which combination of the words to execute the portion of the program on the identified hardware device based on performance efficiency and convert the predicted combination of the words to corresponding numeric values for executing the portion of the program on the identified hardware device.

公开(公告)号：US20240220409A1

公开(公告)日：2024-07-04

申请号：US18090249

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Alan D. Smith ,  Chintan S. Patel ,  William L. Walker

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1024

Abstract: The disclosed computer-implemented method includes partitioning a cache structure into a plurality of cache partitions designated by a plurality of cache types, forwarding a memory request to a cache partition corresponding to a target cache type of the memory request, and performing, using the cache partition, the memory request. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240220336A1

公开(公告)日：2024-07-04

申请号：US18147081

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  Khaled Hamidouche ,  Brandon K Potter ,  Rohit Shahaji Zambre

IPC: G06F9/54 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F9/54 ,  G06F9/5044 ,  G06F15/17356

Abstract: In accordance with described techniques for PE-centric all-to-all communication, a distributed computing system includes processing elements, such as graphics processing units, distributed in clusters. An all-to-all communication procedure is performed by the processing elements that are each configured to generate data packets in parallel for all-to-all data communication between the clusters. The all-to-all communication procedure includes a first stage of intra-cluster parallel data communication between respective processing elements of each of the clusters; a second stage of inter-cluster data exchange for all-to-all data communication between the clusters; and a third stage of intra-cluster data distribution to the respective processing elements of each of the clusters.

公开(公告)号：US20240220297A1

公开(公告)日：2024-07-04

申请号：US18090740

申请日：2022-12-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： David Kaplan ,  Jelena Ilic ,  Nippon Raval ,  Philip Ng

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/45545 ,  G06F2009/45579 ,  G06F2009/45587

Abstract: Techniques for implementing programmable control by a guest virtual machine (VM) of interrupts at a processing system using a guest owned backing page are disclosed. The VM programs a guest owned backing page (e.g., a data structure in memory) that designates particular interrupts that are to be blocked. In response to detecting a designated interrupt, system hardware or software blocks the interrupt, rather than executing an interrupt handler to process the interrupt. The VM is thereby able to protect confidential information and program behavior with less risk of a malicious hypervisor failing to protect the VM from, e.g., unexpected or unwanted interrupts, thereby improving overall system security and predictability.

公开(公告)号：US20240220247A1

公开(公告)日：2024-07-04

申请号：US18148873

申请日：2022-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Vadim Vadimovich Nikiforov ,  Yasuko Eckert ,  Bradford Michael Beckmann

IPC: G06F9/30

CPC classification number: G06F9/30127 ,  G06F9/30134

Abstract: Permute instructions for register-based lookups is described. In accordance with the described techniques, a processor is configured to perform a register-based lookup by retrieving a first result from a first lookup table based on a subset of bits included in an index of a destination register, retrieving a second result from a second lookup table based on the subset of bits included in the index of the destination register, selecting the first result or the second result based on a bit in the index of the destination register that is excluded from the subset of bits, and overwriting data included in the index of the destination register using a selected one of the first result or the second result.

公开(公告)号：US20240220115A1

公开(公告)日：2024-07-04

申请号：US18148091

申请日：2022-12-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PAUL BLINZER ,  DAVID LIVINGSTAIN ZIMAN

IPC: G06F3/06 ,  G06F12/0862 ,  G06T1/20 ,  G06T11/00

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0862 ,  G06T1/20 ,  G06T11/001 ,  G06F2212/1024 ,  G06F2212/602 ,  G06T2210/36

Abstract: An apparatus includes a co-processor that provides process operations for a first processor, such as a host processor, that executes one or more applications. The co-processor issues a data load request to a request command queue controlled by a non-volatile memory system, that loads a subset of prestored data from a prestored set of data, such as file data of an application, that is stored in a cache buffer in the non-volatile memory system or system memory, for an operation performed by the co-processor. The co-processor uses the loaded subset of prestored data for the operation. In certain implementations, the co-processor issues the data load request as a direct memory access (DMA) load request for the cache buffer. The prestored set of data includes a prestored set of data from a file storage system. Associated methods are also disclosed.