公开(公告)号：US20160062378A1

公开(公告)日：2016-03-03

申请号：US14469975

申请日：2014-08-27

Applicant: Analog Devices Technology

Inventor： Miguel A. Ruiz ,  Jose Tejada Gomez

IPC: G05F1/618

CPC classification number: H02M3/07 ,  G05F1/618

Abstract: A switched capacitor voltage converter is provided that includes an array of switches configured to alternately switch multiple capacitors between a charge configuration in which the multiple capacitors are coupled in series with each other and in parallel with the source voltage and a discharge configuration in which a first set of capacitors having n capacitors are coupled in parallel with each other and in series with the load and a second set of capacitors having m capacitors coupled in parallel with the load.

Abstract translation: 提供了一种开关电容器电压转换器，其包括开关阵列，其被配置为在其中多个电容器彼此串联并且与源极电压并联的电荷配置之间交替地切换多个电容器，以及放电配置，其中第一 具有n个电容器的电容器组彼此并联并与负载串联耦合，并且具有与负载并联耦合的m个电容器的第二组电容器。

公开(公告)号：US09246669B2

公开(公告)日：2016-01-26

申请号：US14285415

申请日：2014-05-22

Applicant: Analog Devices Technology

Inventor： Muhammad Kalimuddin Khan ,  Philip E. Quinlan ,  Kenneth J. Mulvaney

IPC: H04L27/10 ,  H04L7/033

CPC classification number: H04L7/033 ,  H04L7/0083 ,  H04L7/046 ,  H04L7/10 ,  H04L27/0008 ,  H04L27/10 ,  H04L27/106

Abstract: Apparatus and method for acquiring and tracking a data signal are disclosed. Two different CDR circuits are configured to acquire and track data based on two different modulation schemes. While in the acquisition mode, the first CDR circuit may acquire data signal by sampling the signal at a reduced clock rate and handover to the second CDR circuit when a preamble is found. Also in the acquisition mode, the data acquisition and tracking circuit may determine the power level of the preamble signal and dynamically adjust the threshold level for the tracking period upon finding of the preamble.

Abstract translation: 公开了用于获取和跟踪数据信号的装置和方法。 两个不同的CDR电路被配置为基于两种不同的调制方案来获取和跟踪数据。 在采集模式中，第一CDR电路可以通过以降低的时钟速率对信号进行采样来获得数据信号，并且当发现前导码时切换到第二CDR电路。 同样在采集模式中，数据采集和跟踪电路可以确定前导码信号的功率电平，并且在寻找前导码时动态地调整跟踪周期的阈值电平。

公开(公告)号：US20150242334A1

公开(公告)日：2015-08-27

申请号：US14187058

申请日：2014-02-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Gregory M. Yukna

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0637 ,  G06F13/1668 ,  Y02D10/14

Abstract: In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Abstract translation: 在一个示例中，本文公开了配置用于可中断原子排他存储器操作的处理器。 例如，负载独占（LDEX）可以后跟存储排他（STREX），两者一起形成一个原子。 为了方便及时处理中断，STREX操作分为两部分。 STREX_INIT不可中断，但具有确定的执行时间，因为它需要固定数量的时钟周期。 STREX_INIT将值发送到内存总线。 之后是一个STREX_SYNC操作，轮询一个标志是否返回值可用。 STREX_SYNC是可中断的，并且公开了用于确定在从中断返回时是否已经破坏操作的原子性的方法。 如果原子性被破坏，则指令失败，而如果保留原子性，则指令完成。

公开(公告)号：US09099932B2

公开(公告)日：2015-08-04

申请号：US13735481

申请日：2013-01-07

Applicant: Analog Devices Technology

Inventor： Yingyang Ou ,  Renjian Xie ,  Huailiang Sheng

IPC: H02M3/335 ,  H02M1/40 ,  H02M7/48

CPC classification number: H02M1/08 ,  H02M1/40 ,  H02M3/33507 ,  H02M3/33576 ,  H02M2007/4803 ,  H03K17/56

Abstract: A duty cycle balance module (DCBM) for use with a switch mode power converter. One possible half-bridge converter embodiment includes a transformer driven to conduct current in first and second directions by first and second signals during and second half-cycles, respectively. A current limiting mechanism adjusts the duty cycles of the first and second signals when a sensed current exceeds a predetermined limit threshold. The DCBM receives signals representative of the duty cycles which would be used if there were no modification by the current limiting mechanism and signals Dact—1 and Dact—2 representative of the duty cycles that are actually used for the first and second signals, and outputs signals Dbl—1 and Dbl—2 which modify signals Dact—1 and Dact—2 as needed to dynamically balance the duty cycles of the first and second signals and thereby reduce flux imbalance in the transformer that might otherwise arise.

Abstract translation: 用于开关模式功率转换器的占空比平衡模块（DCBM）。 一个可能的半桥转换器实施例包括分别被驱动以在第一和第二方向通过第一和第二信号在第一和第二半周期期间传导电流的变压器。 当感测电流超过预定极限阈值时，电流限制机构调节第一和第二信号的占空比。 DCBM接收代表占空比的信号，如果没有通过电流限制机制进行修改，并且表示实际用于第一和第二信号的占空比的Dact-1和Dact-2信号，以及输出 信号Dbl-1和Dbl-2，其根据需要修改信号Dact-1和Dact-2，以动态平衡第一和第二信号的占空比，从而减少可能出现的变压器中的通量不平衡。

公开(公告)号：US20150170911A1

公开(公告)日：2015-06-18

申请号：US14108035

申请日：2013-12-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Paul Martin Lambkin ,  Padraig L. Fitzgerald ,  Bernard Patrick Stenson ,  Raymond C. Goggin ,  Seamus A. Lynch ,  William A. Lane

IPC: H01L21/02

CPC classification number: H01L21/02524 ,  H01H59/0009 ,  H01H2059/0018 ,  H01L21/02002 ,  H01L21/02373 ,  H01L21/322

Abstract: A silicon substrate is provided that may facilitate the formation of RF components more cheaply by using a silicon layer formed by the Czochralski process, and having a carrier life time killing layer deposited on the silicon layer.

Abstract translation: 提供硅衬底，其可以通过使用由Czochralski工艺形成的硅层并且具有沉积在硅层上的载流子寿命消除层，更便宜地形成RF部件。

公开(公告)号：US20150162837A1

公开(公告)日：2015-06-11

申请号：US14100463

申请日：2013-12-09

Applicant: Analog Devices Technology

Inventor： Jun Duan ,  Liuqing Yang ,  Xudong Huang ,  Zhijie Zhu ,  Renjian Xie

IPC: H02M3/335

CPC classification number: H02M3/337 ,  H02M3/33569 ,  H02M3/33592 ,  Y02B70/1475

Abstract: A power converter can include an electrical isolation circuit between input and output nodes. An input signal monitor node can be provided, such as on a converter output side of the isolation circuit. In an example, a peak detection circuit can be coupled to the input signal monitor node. The output node of the power converter can be configured to supply an output power signal that is a function of an input signal at the input node. The power converter can include multiple, independently-switchable switches at one or more of the input and output sides of the isolation circuit. In an example, the power converter with the input signal monitor node can be configured as a bias supply to provide power, at the output node, to a controller circuit for a main stage power converter circuit.

Abstract translation: 功率转换器可以包括输入和输出节点之间的电隔离电路。 可以提供输入信号监视器节点，例如在隔离电路的转换器输出侧。 在一个示例中，峰值检测电路可以耦合到输入信号监视节点。 功率转换器的输出节点可以被配置为提供作为输入节点处的输入信号的函数的输出功率信号。 功率转换器可以在隔离电路的一个或多个输入和输出侧包括多个可独立切换的开关。 在一个示例中，具有输入信号监视器节点的功率转换器可以被配置为偏置电源，以在输出节点向主级功率转换器电路的控制器电路提供功率。

公开(公告)号：US09048734B2

公开(公告)日：2015-06-02

申请号：US13782223

申请日：2013-03-01

Applicant: Analog Devices Technology

Inventor： Song Qin

IPC: G05F1/00 ,  H02M1/32 ,  H02M3/158

CPC classification number: H02M1/32 ,  H02M3/1588 ,  Y02B70/1466

Abstract: A negative current protection system for a low side switching converter FET, for use with a switching converter arranged to operate high and low side FETs connected to an output inductor to produce an output voltage. The negative current protection system includes a current sensing circuit which produces an output Vcs that varies with the current in the high side FET, a negative current threshold generator which produces a threshold signal −Ith which represents the maximum negative current to which the low side FET is to be subjected, and a comparison circuit arranged to compare the valley portion of Vcs and -Ith and to set a flag if Vcs

Abstract translation: 一种用于低侧开关转换器FET的负电流保护系统，用于与连接到输出电感器的高低侧FET连接以产生输出电压的开关转换器。 负电流保护系统包括电流检测电路，其产生随着高侧FET中的电流而变化的输出Vcs;产生阈值信号的负电流阈值发生器，其表示低侧FET的最大负电流 并且比较电路被布置为比较Vcs和-Ith的谷部分，并且在开关周期中的预定时间（通常在转换器的消隐时间之后）设置Vcs <-Ith的标志。 当标志置位时，系统优选地通过调节开关FET的操作来减小负电流来进行响应。

公开(公告)号：US09030342B2

公开(公告)日：2015-05-12

申请号：US13945647

申请日：2013-07-18

Applicant: Analog Devices Technology

Inventor： Kevin Cao-Van Lam ,  Richard E. Schreier ,  Donald W. Paterson

IPC: H03M1/10

CPC classification number: H03M3/38 ,  H03M1/1009 ,  H03M3/392 ,  H03M3/424 ,  H03M3/454

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by denormalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value. In some embodiments, the integrated circuit further includes a scaling module configured to scale the component value based on scaling parameters.

Abstract translation: 集成电路包括：组件计算器，被配置为从至少一个应用参数计算高可编程模数转换器（ADC）的至少一个分量值;以及映射模块，被配置为将分量值映射到对应的寄存器设置 基于至少一个工艺参数，其中所述集成电路产生能够编程所述ADC的数字控制信号。 在具体实施例中，组件计算器使用应用参数的归一化表示的代数函数来近似评估至少一个归一化的ADC系数。 通过对归一化的ADC系数进行非归一化来进一步计算分量值。 在另一具体实施例中，组件计算器使用应用参数的代数函数来计算组件值。 在一些实施例中，集成电路还包括缩放模块，其被配置为基于缩放参数来缩放分量值。

公开(公告)号：US20150123828A1

公开(公告)日：2015-05-07

申请号：US14073396

申请日：2013-11-06

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： David Nelson Alldred ,  Jipeng Li ,  Richard E. Schreier ,  Hajime Shibata

IPC: H03M3/00 ,  H03M1/18

CPC classification number: H03M3/442 ,  H03M3/43 ,  H03M3/454

Abstract: In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.

Abstract translation: 在一个示例实现中，本公开提供了一种在连续时间Σ-Δ模数转换器中使用的环路滤波器。 具体地，在一系列运算放大器积分器中的第一运算放大器的输入处提供电容反馈数模转换器路径。 在第一运算放大器的输入处的电容反馈数模转换器减少了第一运算放大器的输出处的信号内容，从而减小了第一运算放大器的输出摆幅。 输出摆幅的减小提供了更有效的环路滤波器。

公开(公告)号：US08975953B2

公开(公告)日：2015-03-10

申请号：US13793543

申请日：2013-03-11

Applicant: Analog Devices Technology

Inventor： Patrick J. Meehan ,  Mark T. Kelly ,  Christopher Peter Hurrell ,  Thomas Anthony Conway ,  Donal O'Sullivan ,  Michael Hennessy ,  William Hunt

IPC: H03K3/01 ,  H03K17/00

CPC classification number: H03H21/0007 ,  G06F1/26 ,  H03K17/00 ,  H03K17/161 ,  H03M1/0626 ,  H03M1/12

Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Abstract translation: 一种信号处理装置，包括在第一时间段内执行信号处理功能的电路，所述信号处理装置包括或者与所述信号处理装置的电源中的开关或滤波器相关联，以便断开所述信号处理装置 信号处理装置，或者在与第一时间段的至少一部分一致的第二时间段期间对电源进行滤波。