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    Resistive memory devices including selected reference memory cells
    92.
    发明授权
    Resistive memory devices including selected reference memory cells 失效
    电阻式存储器件包括所选择的参考存储单元

    公开(公告)号：US07672155B2

    公开(公告)日：2010-03-02

    申请号：US12265941

    申请日：2008-11-06

    Applicant: Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    Inventor： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC: G11C11/00

    CPC classification number: G11C11/1675 ,  G11C11/1673

    Abstract: A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.

    Abstract translation: 磁存储单元阵列器件可以包括在多个第一和第二存储器单元之间延伸的第一电流源线，该第一和第二存储器单元被配置用于相应的同时编程，并且被配置为进行用于写入多个第一和第二存储器单元之一的足够的编程电流，第一电流 源极晶体管，耦合到第一电流源线和字线，编程导体，其耦合到第一电流源晶体管并且延伸跨越耦合到多个第一和第二存储器单元中的一个的位线，被配置为导通编程电流 耦合到编程导体并被配置为将编程电流从编程导体切换到第二电流源晶体管输出的第二电流源晶体管，与多个第一和第二晶体管中的一个相邻延伸的第二电流源极线 与第一电流源线相对的存储单元，af 第一偏置电路，被配置为将第一偏置电压施加到在读取操作期间被选择访问的第一或第二存储器单元;以及第二偏置电路，被配置为向读取期间未选择访问的第一或第二存储器单元施加第二偏置电压 操作。

    Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same
    93.
    发明授权
    Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same 有权
    使用二元金属氧化物层作为数据存储材料层的交叉点非易失性存储器件及其制造方法

    公开(公告)号：US07535035B2

    公开(公告)日：2009-05-19

    申请号：US11241604

    申请日：2005-09-30

    Applicant: In-Gyu Baek ,  Moon-Sook Lee

    Inventor： In-Gyu Baek ,  Moon-Sook Lee

    IPC: H01L29/73 ,  H01L21/82

    CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

    Abstract: A cross-point nonvolatile memory device using a binary metal oxide layer as a data storage material layer includes spaced apart doped lines disposed in a substrate. Spaced apart upper electrodes cross over the doped lines such that cross points are formed where the upper electrodes overlap the doped lines. Lower electrodes are disposed at the cross points between the doped lines and the upper electrodes. A binary metal oxide layer is provided between the upper electrodes and the lower electrodes and provided as a data storage material layer. Doped regions are provided between the lower electrodes and the doped lines and form diodes together with the doped lines. The doped regions have an opposite polarity to the doped lines.

    Abstract translation: 使用二元金属氧化物层作为数据存储材料层的交叉点非易失性存储器件包括设置在衬底中的间隔开的掺杂线。 间隔开的上电极在掺杂线上交叉，使得形成交叉点，其中上电极与掺杂线重叠。 下电极设置在掺杂线和上电极之间的交叉点处。 在上部电极和下部电极之间设置二元金属氧化物层，作为数据存储材料层。 掺杂区域设置在下电极和掺杂线之间，并与掺杂线一起形成二极管。 掺杂区域具有与掺杂线相反的极性。

    Bipolar Resistive Memory Device Having Tunneling Layer
    96.
    发明申请
    Bipolar Resistive Memory Device Having Tunneling Layer 审中-公开
    具有隧道层的双极电阻存储器件

    公开(公告)号：US20080211036A1

    公开(公告)日：2008-09-04

    申请号：US12037400

    申请日：2008-02-26

    Applicant: Jin Shi Zhao ,  Jang-eun Lee ,  In-gyu Baek ,  Se-chung Oh ,  Kyung-tae Nam ,  Eun-kyung Yim

    Inventor： Jin Shi Zhao ,  Jang-eun Lee ,  In-gyu Baek ,  Se-chung Oh ,  Kyung-tae Nam ,  Eun-kyung Yim

    IPC: H01L29/8605 ,  H01C1/012

    CPC classification number: H01L27/115 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146

    Abstract: A nonvolatile memory device includes a semiconductor substrate, a first electrode on the semiconductor substrate, a resistive layer on the first electrode, a second electrode on the resistive layer and at least one tunneling layer interposed between the resistive layer and the first electrode and/or the second electrode. The resistive layer and the tunneling layer may support transition between first and second resistance states responsive to first and second voltages applied across the first and second electrodes. The first and second voltages may have opposite polarities.

    Abstract translation: 非易失性存储器件包括半导体衬底，半导体衬底上的第一电极，第一电极上的电阻层，电阻层上的第二电极和介于电阻层和第一电极之间的至少一个隧道层和/或 第二电极。 电阻层和隧道层可以响应于施加在第一和第二电极上的第一和第二电压来支持第一和第二电阻状态之间的转变。 第一和第二电压可以具有相反的极性。

    Non-Volatile Memory Devices with Discrete Resistive Memory Material Regions and Methods of Fabricating the Same
    98.
    发明申请
    Non-Volatile Memory Devices with Discrete Resistive Memory Material Regions and Methods of Fabricating the Same 审中-公开
    具有离散电阻记忆材料区域的非易失性存储器件及其制造方法

    公开(公告)号：US20080128853A1

    公开(公告)日：2008-06-05

    申请号：US11939041

    申请日：2007-11-13

    Applicant: Suk-hun Choi ,  In-gyu Baek ,  Jun-young Lee ,  Jung-hyeon Kim ,  Chang-ki Hong ,  Yoon-ho Son

    Inventor： Suk-hun Choi ,  In-gyu Baek ,  Jun-young Lee ,  Jung-hyeon Kim ,  Chang-ki Hong ,  Yoon-ho Son

    IPC: H01L29/00 ,  H01L21/02

    CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L28/20 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

    Abstract: A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.

    Abstract translation: 半导体存储器件包括半导体衬底上的第一导电线，第一导线上的层间绝缘层，层间绝缘层上的第二导线，以及穿过层间绝缘层的孔中的存储单元，其中， 第二导线交叉，存储单元包括设置在孔中并电连接在第一和第二导线之间的分立的电阻性存储器材料区域。 电阻性存储器材料区域可以基本上包含在孔内。 在一些实施例中，电阻性存储器材料区域和层间绝缘层之间的接触基本上限于孔中的层间绝缘层的侧壁。

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