公开(公告)号：US08040733B2

公开(公告)日：2011-10-18

申请号：US12486924

申请日：2009-06-18

Applicant: Jae-hun Jeong ,  Soon-moon Jung ,  Han-soo Kim ,  Jae-hoon Jang

Inventor： Jae-hun Jeong ,  Soon-moon Jung ,  Han-soo Kim ,  Jae-hoon Jang

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages.

Abstract translation: 非易失性存储器件包括分别连接到第一串存储单元晶体管的栅极的第一和第二串存储单元晶体管，相关的第一和第二字线，其中相应的第一和第二字线被连接以共同接收偏置电压。 非易失性存储器件还包括连接到第一和第二串的虚拟单元晶体管，以及被配置为接收不同偏置电压的第一和第二虚拟字线。

公开(公告)号：US20110024816A1

公开(公告)日：2011-02-03

申请号：US12644976

申请日：2009-12-22

Applicant: Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

Inventor： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

Abstract: A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region.

Abstract translation: 一种具有垂直通道结构的闪速存储器件。 闪速存储装置包括：具有沿第一方向延伸的表面的基板，具有柱状的沟道区域，并且在与第一方向垂直的第二方向上从基板延伸;栅极介电层，形成在沟道区域周围 ，包括在所述第二方向上依次形成在所述沟道区周围的多个晶体管的存储单元串，其中所述栅介质层设置在所述多个晶体管和所述沟道区之间，并且位线连接到所述多个晶体管中的一个晶体管 并且围绕通道区域的一端的侧壁和上表面，以便直接接触通道区域。

公开(公告)号：US07646664B2

公开(公告)日：2010-01-12

申请号：US11869140

申请日：2007-10-09

Applicant: Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

Inventor： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

Abstract: A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

Abstract translation: 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

公开(公告)号：US20100001337A1

公开(公告)日：2010-01-07

申请号：US12456537

申请日：2009-06-18

Applicant: Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

Inventor： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11551 ,  H01L27/0207 ,  H01L27/0688

Abstract: A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor.

Abstract translation: 半导体存储器件包括：顺序堆叠的第一和第二半导体层; 设置在所述第一半导体层上的至少一个第一存储晶体管; 以及设置在所述第二半导体层上的至少一个第二存储晶体管，其中所述第一存储晶体管的栅电极具有比所述第二存储晶体管宽的宽度。

公开(公告)号：US07602028B2

公开(公告)日：2009-10-13

申请号：US11653890

申请日：2007-01-17

Applicant: Yang-Soo Son ,  Young-Seop Rah ,  Won-Seok Cho ,  Soon-Moon Jung ,  Jae-Hoon Jang ,  Young-Chul Jang

Inventor： Yang-Soo Son ,  Young-Seop Rah ,  Won-Seok Cho ,  Soon-Moon Jung ,  Jae-Hoon Jang ,  Young-Chul Jang

IPC: H01L29/76

CPC classification number: H01L27/115 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.

Abstract translation: NAND闪速存储器件包括下半导体层和位于下半导体层上的上半导体层，位于下半导体层中的第一漏区和第一源区，以及位于下半导体层中的第二漏区和第二源区 上半导体层。 第一栅极结构位于下半导体层上，第二栅极结构位于上半导体层上。 位线位于上半导体层上方，并且至少一位位线插头连接在位线和第一漏极区之间，其中至少一位位线插头延伸穿过位于上半导体层中的漏极通孔。

公开(公告)号：US20090251962A1

公开(公告)日：2009-10-08

申请号：US12418821

申请日：2009-04-06

Applicant: Jong-In Yun ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jun-Beom Park ,  Jae-Hun Jeong

Inventor： Jong-In Yun ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jun-Beom Park ,  Jae-Hun Jeong

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/3427 ,  H01L27/11551

Abstract: A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.

Abstract translation: 提供具有多个层的三维存储器件的驱动方法。 选择其中一个图层。 所选择的层的阱被第一阱电压偏置。 字线电压被施加到所选层的选定字线。 未选择的层的阱以比第一阱电压高的第二阱电压偏置。

公开(公告)号：US07521715B2

公开(公告)日：2009-04-21

申请号：US11032725

申请日：2005-01-11

Applicant: Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

Inventor： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC: H01L27/108

CPC classification number: H01L27/11 ,  H01L27/1108 ,  Y10S257/903

Abstract: A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

Abstract translation: 静态随机存取存储器（SRAM）器件可以包括在其中具有源极/漏极区域的半导体衬底上的体MOS晶体管，体MOS晶体管上的绝缘层，以及在其中具有源极/漏极区域的薄膜晶体管 在体MOS晶体管上方的绝缘层上。 器件还可以包括在体MOS晶体管和薄膜晶体管之间的多层插头。 多层插头可以包括直接在体MOS晶体管的源极/漏极区域上并延伸穿过绝缘层的至少一部分的半导体插头，以及直接在薄膜的源极/漏极区域上的金属插塞 晶体管和半导体插头并延伸穿过绝缘层的至少一部分。 还讨论了相关方法。

公开(公告)号：US20080185648A1

公开(公告)日：2008-08-07

申请号：US12024459

申请日：2008-02-01

Applicant: Jae Hun Jeong ,  Kim-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

Inventor： Jae Hun Jeong ,  Kim-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC: H01L27/12

CPC classification number: H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

Abstract translation: 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

公开(公告)号：US07387919B2

公开(公告)日：2008-06-17

申请号：US11281346

申请日：2005-11-16

Applicant: Kun-Ho Kwak ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim

Inventor： Kun-Ho Kwak ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L27/092

Abstract: In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic single crystalline semiconductor plug as a seed layer. When the recessed single crystalline semiconductor plug is doped with impurities having the same conductivity type as the node impurity region, a peripheral impurity region is prevented from being counter-doped. As a result, it is possible to implement a high performance semiconductor device that requires a single crystalline thin film transistor as well as a node contact structure with ohmic contact.

Abstract translation: 在一个实施例中，使用使用节点杂质区域作为种子层的选择性外延生长工艺，形成本征单晶半导体插塞以穿过下绝缘层，并且在下绝缘层上形成单晶体半导体本体图案，使用 本征单晶半导体插头作为种子层。 当嵌入的单晶半导体插件掺杂有与节点杂质区相同的导电类型的杂质时，防止外围杂质区域被反掺杂。 结果，可以实现需要单晶薄膜晶体管的高性能半导体器件以及具有欧姆接触的节点接触结构。

公开(公告)号：US20080108213A1

公开(公告)日：2008-05-08

申请号：US11654133

申请日：2007-01-17

Applicant: Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

Inventor： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC: H01L21/4763 ,  H01L21/3205

CPC classification number: H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

Abstract translation: 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。