公开(公告)号：US11218659B2

公开(公告)日：2022-01-04

申请号：US16708135

申请日：2019-12-09

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Chengcheng Xu ,  Rui Wang ,  Bi Yuan ,  Liang Zuo

IPC: H04N5/378 ,  H04N5/3745 ,  H04N5/374 ,  H04N5/376 ,  H04N5/369 ,  H04N5/351

Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.

公开(公告)号：US11206368B2

公开(公告)日：2021-12-21

申请号：US16882254

申请日：2020-05-22

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Chun-Hsiang Chang ,  Zejian Wang ,  Chao-Fang Tsai ,  Jingwei Lai

IPC: H04N5/369 ,  H04N5/372 ,  H04N5/376 ,  H04N5/378 ,  H04N5/374

Abstract: A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.

公开(公告)号：US11206039B1

公开(公告)日：2021-12-21

申请号：US17127499

申请日：2020-12-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara

IPC: H03M1/56 ,  H03K5/08 ,  H04N5/3745 ,  H03M1/46 ,  H03K5/24

Abstract: A comparator includes a second stage coupled between a first stage and a third stage. The second stage includes a first transistor coupled to be switched in response to a first output signal coupled to be received from the first stage. The first transistor is coupled generate a second output signal coupled to be received by the third stage. A second transistor is coupled to the first transistor. The first and second transistors are coupled between a first supply voltage and a reference voltage. A second stage current of the second stage is conducted through the first transistor and the second transistor. The second transistor is coupled to be switched in response to a third output signal coupled to be received from the third stage in response to the second output signal.

公开(公告)号：US20210392286A1

公开(公告)日：2021-12-16

申请号：US16900576

申请日：2020-06-12

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Rui Wang ,  John Brummer ,  Shan Chen

IPC: H04N5/378 ,  H04N5/355 ,  H04N5/365

Abstract: A pixel cell readout circuit includes a bitline input stage coupled to a bitline to receive an image signal from a pixel cell. A capacitor ratio circuit is coupled to the bitline input stage. A gain of the bitline input stage is responsive to a capacitor ratio provided by the capacitor ratio circuit to the bitline input stage. A switch control circuit is coupled to receive a gain signal. The switch control circuit is coupled to generate a randomized pattern selection signal coupled to be received by the capacitor ratio circuit to select the capacitor ratio provided by the capacitor ratio circuit in response to the gain signal.

公开(公告)号：US20210377435A1

公开(公告)日：2021-12-02

申请号：US16886473

申请日：2020-05-28

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Keiji Mabuchi ,  Zhe Gao

IPC: H04N5/235 ,  H01L27/092 ,  H04N5/345 ,  H01L27/146

Abstract: A pixel cell includes a first subpixel and a plurality of second subpixels. Each subpixel includes a photodiode to photogenerate image charge in response to incident light. Image charge is transferred from the first subpixel to a floating diffusion through a first transfer transistor. Image charge is transferred from the plurality of second subpixels to the floating diffusion through a plurality of second transfer transistors. An attenuation layer is disposed over the first subpixel. The first subpixel receives the incident light through the attenuation layer. The plurality of second subpixels receive the incident light without passing through the attenuation layer. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A capacitor is coupled to the DFD transistor.

公开(公告)号：US11181419B2

公开(公告)日：2021-11-23

申请号：US16155616

申请日：2018-10-09

Applicant: OmniVision Technologies, Inc.

Inventor： Trygve Willassen ,  Olivier Bulteel ,  Trung Nguyen ,  Robert Johansson

IPC: G01S17/894 ,  G01J1/46 ,  G01J1/42 ,  G01S17/08 ,  G01S7/4865 ,  G01S7/4863 ,  G01J1/44

Abstract: A threshold detection circuit includes a plurality of capacitors. A plurality of switching circuits is coupled to the capacitors such that a first end of each of the capacitors is coupled to a corresponding photon sensor during detection intervals, and the first end of each capacitor is coupled to a variable initialization value during reset intervals. A threshold number of the capacitors are initialized to a first value and the remaining capacitors are initialized to a second value during reset intervals. A comparator is coupled to a second of the capacitors to generate a detection event in response to the threshold number of photon sensors sensing one or more incident photons during detection intervals.

公开(公告)号：US20210352234A1

公开(公告)日：2021-11-11

申请号：US16870687

申请日：2020-05-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Badrinath Padmanabhan ,  Boyd Fowler ,  Alireza Bonakdar ,  Richard Mann

IPC: H04N5/369 ,  H04N5/378 ,  H04N5/3745 ,  H01L27/146

Abstract: In some embodiments, an imaging system is provided. The imaging system comprises an image sensor, a light source, control circuitry, and function logic. The image sensor comprises a pixel array that includes a plurality of polarization pixel cells and a plurality of time-of-flight pixel cells. The light source is configured to emit light pulses to an object. The control circuitry is coupled to the light source and the pixel array, and is configured to synchronize a timing of the emission of the light pulses with sensing of photons reflected from the object by the plurality of time-of-flight pixel cells to generate depth information. The function logic is configured to determine a set of ambiguous surface normals using signals generated by the plurality of polarization pixel cells, and to disambiguate the set of ambiguous surface normals using the depth information to generate a three-dimensional shape image.

公开(公告)号：US20210351768A1

公开(公告)日：2021-11-11

申请号：US16867399

申请日：2020-05-05

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Liang Zuo ,  Nijun Jiang ,  Min Qu ,  Xuelian Liu

IPC: H03K4/06 ,  H03M3/00 ,  H03M1/56 ,  H04N5/378

Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

公开(公告)号：US20210343882A1

公开(公告)日：2021-11-04

申请号：US16863771

申请日：2020-04-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Mamoru Iesaka ,  Woon Il Choi ,  Sohei Manabe

IPC: H01L31/028 ,  H01L27/146

Abstract: Low noise silicon-germanium (SiGe) image sensor. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor substrate. The photodiodes of an individual pixel are configured to receive an incoming light through an illuminated surface of the semiconductor substrate. The semiconductor substrate includes a first layer of semiconductor material having silicon (Si); and a second layer of semiconductor material having silicon germanium (Si1-xGex). A concentration x of Ge changes gradually through at least a portion of thickness of the second layer. Each photodiode includes a first doped region extending through the first layer of semiconductor material and the second layer of semiconductor material; and a second doped region extending through the first layer of semiconductor material and the second layer of semiconductor material.

公开(公告)号：US20210337169A1

公开(公告)日：2021-10-28

申请号：US16855857

申请日：2020-04-22

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Qingfei Chen ,  Rui Wang ,  Wei Wei Wang ,  Zhiyong Zhan ,  Xin Wang ,  Qingwei Shan ,  Kenny Geng

IPC: H04N9/04 ,  H04N5/369 ,  H04N5/3745 ,  H04N5/378

Abstract: An imaging device includes groupings of photodiodes having four photodiodes. A transfer transistor is between each photodiode and a floating diffusion. Each floating diffusion is coupled to up to two photodiodes per grouping at a time through transfer transistors. A buffer transistor is coupled to each floating diffusion. The buffer transistors may be in a first or second grouping of buffer transistors. A first bit line is coupled to up to two buffer transistors of the first grouping and a second bit line is coupled to up to two buffer transistors of the second grouping of buffer transistors at a time. A color filter array including a plurality of groupings of color filters is disposed over respective photodiodes of the photodiode array, wherein each grouping of color filters includes four color filters having a same color, wherein each grouping of color filters overlaps two groupings of photodiodes.