公开(公告)号：US20150055428A1

公开(公告)日：2015-02-26

申请号：US13972785

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G06F12/0875 ,  G06F1/24 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0638 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/44505 ,  G06F11/1008 ,  G06F11/1068 ,  G06F12/0646 ,  G06F12/0692 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/128 ,  G06F2212/1008 ,  G06F2212/1012 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/453 ,  G06F2212/601 ,  G06F2212/62 ,  G06F2212/69 ,  G11C17/16 ,  G11C17/18 ,  G11C29/52 ,  G11C29/802

Abstract: An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory.

Abstract translation: 一种装置具有熔丝阵列，高速缓冲存储器和核心。 熔丝阵列设置在芯片上，其中编程了配置数据。 熔丝阵列包括第一多个保险丝和第二多个保险丝。 第一组多个保险丝存储压缩缓存校正数据。 第二多个保险丝存储压缩的熔丝校正数据，该数据指示与其先前存储的状态将改变其状态的第一组多个保险丝内的一个或多个保险丝对应的位置和值。 磁芯设置在芯片上，其中每个磁芯在上电/复位时访问熔丝阵列。 每个核心包括高速缓存熔丝解压缩器，其根据位置和值改变状态，解压缩压缩高速缓存校正数据，并分配解压缩的高速缓存校正数据以初始化高速缓冲存储器。

公开(公告)号：US08952734B2

公开(公告)日：2015-02-10

申请号：US13850666

申请日：2013-03-26

Applicant: Via Technologies, Inc.

Inventor： Yeong-Sheng Lee

IPC: H03L7/00 ,  H03L7/14 ,  H04L27/00

CPC classification number: H03L7/14 ,  H03L7/0816 ,  H03L7/0891 ,  H03L7/099 ,  H04L27/00

Abstract: A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops.

Abstract translation: 提供信号发生装置以产生具有恒定频率的输出信号。 信号发生装置包括频率控制电路和电压控制延迟线。 频率控制电路包括脉冲发生器，根据比较结果信号的转变，根据参考信号的转变和比较脉冲信号产生参考脉冲信号，以重新形成参考信号和比较结果信号 转换成适合时钟和复位触发器的窄脉冲。

公开(公告)号：US20150012549A1

公开(公告)日：2015-01-08

申请号：US14271458

申请日：2014-05-07

Applicant: VIA Technologies, Inc.

Inventor： Guo-Feng Zhang ,  Yi-Fei Zhu

IPC: G06F17/30

CPC classification number: G06F17/3087 ,  G06F7/08 ,  G06F17/30675

Abstract: A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving corresponding keyword rankings of the plurality of keywords by a search engine; searching corresponding keyword categories of the plurality of keywords; and generating a sort algorithm based on the plurality of keywords, the keyword ranking and the keyword category of each of the plurality of keywords, and a current ranking of each of the plurality of data documents, wherein the sort algorithm is used to calculate a predicting ranking of another data document and to sort the another data document.

Abstract translation: 提供数据文件的分类方法，适用于电子设备。 分类方法包括以下步骤：从多个数据文档的内容中检索多个关键字; 通过搜索引擎检索所述多个关键字的对应关键字排名; 搜索所述多个关键字的对应关键词类别; 以及基于所述多个关键词，所述多个关键字中的每一个的关键字排序和关键字类别以及所述多个数据文档中的每一个的当前排名来生成排序算法，其中所述排序算法用于计算预测 排序另一个数据文件并排序另一个数据文档。

公开(公告)号：US08911291B2

公开(公告)日：2014-12-16

申请号：US13685617

申请日：2012-11-26

Applicant: VIA Technologies, Inc.

Inventor： Steve Shu Liu

IPC: A63F9/24

CPC classification number: G07F17/3227 ,  G07F17/3211 ,  G07F17/3225

Abstract: A display system and a display method for video walls are provided. The display system includes at least one server and a plurality of player devices. Each server renders an image and transmits the image to a network. The player devices are coupled to the at least one server through the network. Each player device receives the image or a part of the image rendered by one of the at least one server, and determines a synchronization time together with at least one of the other player devices. Each player device uses a display of a video wall to simultaneously display the image or the part of the image at the synchronization time.

Abstract translation: 提供了一种用于视频墙的显示系统和显示方法。 显示系统包括至少一个服务器和多个播放器设备。 每个服务器呈现图像并将图像传输到网络。 播放器设备通过网络耦合到至少一个服务器。 每个播放器设备接收图像或由至少一个服务器中的一个呈现的图像的一部分，并且与至少一个其他播放器设备一起确定同步时间。 每个播放器设备使用视频墙的显示器在同步时间同时显示图像或图像的一部分。

公开(公告)号：US20140361828A1

公开(公告)日：2014-12-11

申请号：US14202313

申请日：2014-03-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： James R. Lundberg

IPC: H03K17/687

CPC classification number: H03K19/0008

Abstract: An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.

Abstract translation: 包括全局电源总线，门控电源总线，耦合到门控电源总线的功能电路，存储编程控制参数的可编程器件和数字电源门控系统的集成电路。 数字电源门控系统包括门控设备和电源门控控制系统。 每个选通装置耦合在全局和门控供电总线之间，并且每个具有控制终端。 电源门控控制系统控制数字控制值以控制门控设备的激活。 电源门控控制系统被配置为通过调整数字控制值来执行电力门控操作，以控制门控电源总线相对于全局电源总线的电压的电压。 电源门控操作可以使用编程的控制参数进行调整。 可编程器件可以是保险丝阵列或用编程控制参数编程的存储器。

公开(公告)号：US08886855B2

公开(公告)日：2014-11-11

申请号：US13747140

申请日：2013-01-22

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/00 ,  G06F17/30 ,  G06F13/42

CPC classification number: G06F17/30581 ,  G06F13/4217

Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.

Abstract translation: 补偿同步数据总线上的未对准的装置。 该装置包括复制分发网络，位延迟控制元件和同步延迟接收器。 复制分发网络接收第一信号，并且生成第二信号，其中复制分发网络包括用于选通的径向分布网络的复制传播特性。 比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。 同步延迟接收器耦合到位延迟控制元件，并且被配置为接收多个径向分布的选通信号和数据位中的第一个，并被配置为延迟数据位的登记传播时间。

公开(公告)号：US20140306736A1

公开(公告)日：2014-10-16

申请号：US13963446

申请日：2013-08-09

Applicant: Via Technologies, Inc.

Inventor： Hung-Yi KUO

IPC: H03K19/0175

CPC classification number: H03K19/017581

Abstract: A state machine circuit switching between multiple states is provided. The state machine circuit has: a state patch circuit for generating a patched predicted state value, a patched output value, and a selection signal according to a current state value and at least one of a second input signal, a predicted state value, and an output value of the state machine circuit; a first selection circuit for outputting the patched predicted state or the predicted state to a register according to the selection signal; and a second selection circuit for outputting the patched output value or the output value according to the selection signal, wherein the predicted state value and the output value are generated according to a first input signal and the current state value of the state machine circuit, and the predicted state value and the output value are not generated according to the second input signal.

Abstract translation: 提供了在多种状态之间切换的状态机电路。 状态机电路具有：状态补丁电路，用于根据当前状态值和第二输入信号，预测状态值和第二输入信号中的至少一个产生修补预测状态值，修补输出值和选择信号 状态机电路的输出值; 第一选择电路，用于根据选择信号将修补的预测状态或预测状态输出到寄存器; 以及第二选择电路，用于根据选择信号输出修补的输出值或输出值，其中根据第一输入信号和状态机电路的当前状态值产生预测状态值和输出值，以及 根据第二输入信号不产生预测状态值和输出值。

公开(公告)号：US20140298060A1

公开(公告)日：2014-10-02

申请号：US14077740

申请日：2013-11-12

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Terry Parks ,  G. Glenn Henry

IPC: G06F1/32

Abstract: A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

Abstract translation: 处理器包括被配置为支持其指令集体系结构（ISA）特征集的特征的第一和第二相应子集的第一和第二处理核心。 第一个子集小于ISA功能集的所有功能。 第一个和第二个子集是不同的，但它们的联合是ISA功能集的所有功能。 第一核心在由第一核心而不是第二核心执行的同时检测线程，尝试使用不在第一子集中的特征，并且响应地指示从第一核到第二核的切换以执行 线程。 不支持的功能可能是不支持的指令或操作模式。 如果较低性能/功率核心被过度利用或较高性能/功率核心利用不足，也可能产生开关。

公开(公告)号：US20140298053A1

公开(公告)日：2014-10-02

申请号：US14138151

申请日：2013-12-23

Applicant: VIA Technologies, Inc.

Inventor： Yi-Te Chen ,  Terrance Shiyang Shih ,  Hsiao-Chyi Lin

IPC: G06F1/32

CPC classification number: G06F1/325 ,  G06F1/3253 ,  G06F1/3296 ,  Y02D10/151 ,  Y02D10/172

Abstract: A universal serial bus and a control method thereof are provided. Different voltages are respectively provided to circuit groups when a universal serial bus hub is in a suspend state and a normal working state, so as to reduce leakage current.

Abstract translation: 提供通用串行总线及其控制方法。 当通用串行总线集线器处于暂停状态和正常工作状态时，分别向电路组提供不同的电压，以减少漏电流。

公开(公告)号：US20140223041A1

公开(公告)日：2014-08-07

申请号：US13953441

申请日：2013-07-29

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Kuo-Han CHANG ,  Xiaolu YANG

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: An integrated circuit for controlling a slave device is provided. The integrated circuit includes a pin, a micro-controller and an inter integrated circuit (I2C) bus controller coupled between the micro-controller and the pin. The I2C bus controller includes a transceiver unit coupled to the slave device via the pin, and an interface unit coupled between the transceiver unit and the micro-controller. The interface unit includes a start control register and a stop control register. The start control register provides a start signal to the slave device via the transceiver unit when the start control register is programmed by the micro-controller. The stop control register provides a stop signal to the slave device via the transceiver unit when the stop control register is programmed by the micro-controller. The micro-controller programs the stop control register according to an interrupt signal from the interface unit.

Abstract translation: 提供了一种用于控制从设备的集成电路。 该集成电路包括一个引脚，一个微控制器和一个耦合在微控制器和引脚之间的集成电路（I2C）总线控制器。 I2C总线控制器包括经由引脚耦合到从设备的收发器单元和耦合在收发器单元和微控制器之间的接口单元。 接口单元包括启动控制寄存器和停止控制寄存器。 当启动控制寄存器由微控制器编程时，启动控制寄存器通过收发器单元向从设备提供启动信号。 当停止控制寄存器由微控制器编程时，停止控制寄存器通过收发器单元向从设备提供停止信号。 微控制器根据来自接口单元的中断信号对停止控制寄存器进行编程。