公开(公告)号：US07348611B2

公开(公告)日：2008-03-25

申请号：US11112820

申请日：2005-04-22

申请人： Meikei Ieong ,  Qiqing C. Ouyang ,  Kern Rim

发明人： Meikei Ieong ,  Qiqing C. Ouyang ,  Kern Rim

IPC分类号： H01L29/73

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

摘要翻译： 本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。 具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。 通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变， 一个紧张的班轮。 本发明还提供了制造上述半导体结构的方法。

公开(公告)号：US07273800B2

公开(公告)日：2007-09-25

申请号：US10978715

申请日：2004-11-01

申请人： Diane C. Boyd ,  Juan Cai ,  Kevin K. Chan ,  Patricia M. Mooney ,  Kern Rim

发明人： Diane C. Boyd ,  Juan Cai ,  Kevin K. Chan ,  Patricia M. Mooney ,  Kern Rim

IPC分类号： H01L21/265 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/1054 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/7842 ,  Y10S438/938

摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

摘要翻译： 本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。 以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。 通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。 然后在含有受损区域的含Si衬底上形成应变SiGe合金。 然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。 接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

公开(公告)号：US07187059B2

公开(公告)日：2007-03-06

申请号：US10875727

申请日：2004-06-24

申请人： Kevin K. Chan ,  Kathryn W. Guarini ,  Meikel Ieong ,  Kern Rim ,  Min Yang

发明人： Kevin K. Chan ,  Kathryn W. Guarini ,  Meikel Ieong ,  Kern Rim ,  Min Yang

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

摘要： A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described including the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HCL acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a root mean square (RMS) surface roughness of less than 0.1 run.

摘要翻译： 描述了用于导电载体的结构和形成方法，其结合了具有在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此形成PS形态层 正在紧张。 描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃来形成拟态或外延层的步骤，并引入含Si气体 和含Ge的气体。 描述了用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCL酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底 以获得不含杂质的基体表面，均方根（RMS）的表面粗糙度小于0.1nm。

公开(公告)号：US07129548B2

公开(公告)日：2006-10-31

申请号：US10916201

申请日：2004-08-11

申请人： Kevin K. Chan ,  Christian Lavoie ,  Kern Rim

发明人： Kevin K. Chan ,  Christian Lavoie ,  Kern Rim

IPC分类号： H01L29/94

CPC分类号： H01L29/66507 ,  H01L29/6653 ,  H01L29/7833

摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.

公开(公告)号：US20060091377A1

公开(公告)日：2006-05-04

申请号：US10978715

申请日：2004-11-01

申请人： Diane Boyd ,  Juan Cai ,  Kevin Chan ,  Patricia Mooney ,  Kern Rim

发明人： Diane Boyd ,  Juan Cai ,  Kevin Chan ,  Patricia Mooney ,  Kern Rim

IPC分类号： H01L29/06

CPC分类号： H01L29/1054 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/7842 ,  Y10S438/938

摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

摘要翻译： 本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。 以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。 通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。 然后在含有受损区域的含Si衬底上形成应变SiGe合金。 然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。 接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

公开(公告)号：US07034362B2

公开(公告)日：2006-04-25

申请号：US10688692

申请日：2003-10-17

申请人： Kern Rim

发明人： Kern Rim

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/78681 ,  H01L29/78684

摘要： A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source/drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.

摘要翻译： 提供了在各种半导体层之间具有降低的阶梯高度而不会对形成在最上半导体层上的半导体器件的结电容产生不利影响的SOI MOSFET结构及其制造方法。 本发明的结构包括具有位于第二半导体层上的至少一个半导体器件的升高器件区域。 升高的器件区域还包括从第二半导体层向下延伸到位于半导体衬底的上表面上的第一掩埋绝缘体层的源极/漏极结。 该结构还包括具有位于第一半导体层顶部的至少一个半导体器件的凹陷器件区域，第一半导体层位于第一埋入绝缘体的上表面上。 隔离区域将升高的装置区域与凹入装置区域分开。

公开(公告)号：US20060001088A1

公开(公告)日：2006-01-05

申请号：US10883443

申请日：2004-07-01

申请人： Kevin Chan ,  Jack Chu ,  Kern Rim ,  Leathen Shi

发明人： Kevin Chan ,  Jack Chu ,  Kern Rim ,  Leathen Shi

IPC分类号： H01L21/00 ,  H01L31/0392

CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate comprising a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer. Specifically, the method includes forming a first multilayered structure comprising at least a tensile-strained SiGe alloy layer located above a relaxed SiGe alloy layer, wherein the tensile-strained SiGe alloy contains a lower Ge content than the relaxed SiGe alloy layer; bonding the first multilayered structure to an insulating layer of a second multilayered structure on a surface opposite the relaxed SiGe alloy layer; and removing the relaxed SiGe alloy layer.

摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。 具体地说，该方法包括形成至少包含位于松弛SiGe合金层上方的拉伸应变SiGe合金层的第一多层结构，其中拉伸应变SiGe合金含有比松弛SiGe合金层低的Ge含量; 将第一多层结构结合到与松弛SiGe合金层相对的表面上的第二多层结构的绝缘层; 并去除松弛的SiGe合金层。

公开(公告)号：US20050285187A1

公开(公告)日：2005-12-29

申请号：US10930404

申请日：2004-08-31

申请人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

发明人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

IPC分类号： H01L29/10 ,  H01L29/165 ,  H01L29/24 ,  H01L29/76

CPC分类号： H01L29/165 ,  H01L29/1054 ,  H01L29/24 ,  H01L29/7842 ,  H01L29/7843

摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

摘要翻译： 本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。 单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。 单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。 单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。 本发明还提供了用应变诱导隔离区增加双轴应变的方法。 本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

公开(公告)号：US06667528B2

公开(公告)日：2003-12-23

申请号：US10033902

申请日：2002-01-03

申请人： Guy Moshe Cohen ,  Kern Rim ,  Dennis L. Rogers ,  Jeremy Daniel Schaub ,  Min Yang

发明人： Guy Moshe Cohen ,  Kern Rim ,  Dennis L. Rogers ,  Jeremy Daniel Schaub ,  Min Yang

IPC分类号： H01L31058

CPC分类号： H01L31/105 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.

摘要翻译： 光电检测器（及其制造方法）包括半导体衬底，形成在衬底上的埋入绝缘体，形成在埋层绝缘体上的掩埋反射镜，形成在导体上的绝缘体上半导体层（SOI）层， 形成在绝缘体上半导体层中的p型和p型掺杂指，以及与p型掺杂指和n型掺杂指之一的背面接触。

公开(公告)号：US06429061B1

公开(公告)日：2002-08-06

申请号：US09626331

申请日：2000-07-26

申请人： Kern Rim

发明人： Kern Rim

IPC分类号： H01L21336

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66651 ,  Y10S438/933

摘要： A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe layer. These processing steps may be used in conjunction with conventional gate processing steps in forming a strained MOSFET structure.

摘要翻译： 通过包括在衬底的表面上形成松弛的SiGe层的步骤形成应变Si CMOS结构; 在所述松弛SiGe层中形成隔离区和阱注入区; 并在所述松弛的SiGe层上形成应变Si层。 这些处理步骤可以与形成应变MOSFET结构中的常规栅极处理步骤结合使用。