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    Access suppression in a memory device
    96.
    发明授权
    Access suppression in a memory device 有权

    公开(公告)号：US09600179B2

    公开(公告)日：2017-03-21

    申请号：US14446668

    申请日：2014-07-30

    Applicant: ARM Limited

    Inventor： Yew Keong Chong ,  Michael Alan Filippo ,  Gus Yeung ,  Andy Wangkun Chen ,  Sriram Thyagarajan

    IPC: G11C8/08 ,  G06F3/06 ,  G06F1/32 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22

    CPC classification number: G06F3/06 ,  G06F1/3275 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.

    Low power input gating
    97.
    发明授权
    Low power input gating 有权
    低功率输入门控

    公开(公告)号：US09542986B2

    公开(公告)日：2017-01-10

    申请号：US14849902

    申请日：2015-09-10

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Gus Yeung ,  Yew Keong Chong

    IPC: G11C8/18 ,  G11C8/06

    CPC classification number: G11C8/18 ,  G11C5/141 ,  G11C8/06

    Abstract: Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.

    Abstract translation: 本文所描述的各种实现涉及用于实现低功率输入门控的集成电路。 在一个实现中，集成电路可以包括芯片使能装置，其被配置为接收和使用时钟输入信号，以基于芯片使能信号切换存储器的控制输入。 集成电路可以包括被配置为锁存存储器的控制输入的锁存装置。 集成电路可以包括耦合在芯片使能装置和锁存装置之间的锁存使能装置。 锁存使能装置可以被配置为从芯片使能装置接收时钟输入信号，并且使用时钟输入信号基于锁存使能信号来对锁存器件进行门控，以便有选择地将时钟输入信号切换到控制输入 的记忆。

    Level conversion circuit and method
    98.
    发明授权
    Level conversion circuit and method 有权
    电平转换电路及方法

    公开(公告)号：US09379710B2

    公开(公告)日：2016-06-28

    申请号：US14192056

    申请日：2014-02-27

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong

    IPC: H03K5/00 ,  H03K19/0185 ,  H03K19/00

    CPC classification number: H03K19/018507 ,  H03K19/0013

    Abstract: A level conversion circuit is provided for generating an output signal having one of a higher output level and a lower output level in response to an input signal having one of a higher input level and a lower input level. The level conversion circuit has input circuitry which, in response to a transition of the input signal between the higher and lower input levels, output a rising transition of a temporary output signal on the output line towards the higher input level. Output control circuitry detects the rising transition of the temporary output signal and pulls the output signal to the higher output level. This arrangement allows for fast level conversion without a DC leakage path.

    Abstract translation: 提供电平转换电路，用于响应于具有较高输入电平和较低输入电平之一的输入信号，产生具有较高输出电平和较低输出电平之一的输出信号。 电平转换电路具有输入电路，响应于输入信号在较高和较低输入电平之间的转变，输出线路上的临时输出信号向上输入电平的上升转变。 输出控制电路检测临时输出信号的上升转换，并将输出信号拉至较高的输出电平。 这种布置允许在没有DC泄漏路径的情况下进行快速电平转换。

    ACCESS SUPPRESSION IN A MEMORY DEVICE
    99.
    发明申请
    ACCESS SUPPRESSION IN A MEMORY DEVICE 有权
    存储设备中的访问抑制

    公开(公告)号：US20160034403A1

    公开(公告)日：2016-02-04

    申请号：US14446668

    申请日：2014-07-30

    Applicant: ARM Limited

    Inventor： Yew Keong Chong ,  Michael Alan Filippo ,  Gus Yeung ,  Andy Wangkun Chen ,  Sriram Thyagarajan

    IPC: G06F12/08

    CPC classification number: G06F3/06 ,  G06F1/3275 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.

    Abstract translation: 提供了存储器件和操作存储器件的方法。 存储器件包括多个存储单元和访问控制电路。 访问控制被配置为接收访问请求并且响应于访问请求以在多个存储单元中的每一个中发起访问过程。 所述访问控制电路被配置为在所述访问过程已经被启动之后接收访问终止信号，并且响应于所述访问禁止信号来启动访问抑制以抑制所述多个存储单元中的至少一个中的访问过程。 因此，通过响应于访问请求在所有存储单元中启动访问过程，例如， 在不等待对其进行访问过程的特定存储单元的进一步指示的情况下，存储器件的总访问时间保持为低，但是通过使访问过程中的至少一个随后能够被响应于访问被抑制 杀死信号动态功耗的存储器件可以减少。

    Multi-port bitcell architecture
    100.
    发明授权
    Multi-port bitcell architecture 有权

    公开(公告)号：US12300310B2

    公开(公告)日：2025-05-13

    申请号：US17971226

    申请日：2022-10-21

    Applicant: Arm Limited

    Inventor： Vianney Antoine Choserot ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

    IPC: G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

    Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

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