公开(公告)号：US06214660B1

公开(公告)日：2001-04-10

申请号：US09177620

申请日：1998-10-23

申请人： Yasuhiro Uemoto ,  Eigi Fujii ,  Koji Arita ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Masamichi Azuma ,  Atsuo Inoue ,  Yasufumi Izutsu

发明人： Yasuhiro Uemoto ,  Eigi Fujii ,  Koji Arita ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Masamichi Azuma ,  Atsuo Inoue ,  Yasufumi Izutsu

IPC分类号： H01L213205

CPC分类号： H01L27/11502 ,  H01L28/40 ,  H01L28/56

摘要： A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

摘要翻译： 一种用于制造用于集成电路的电容器的方法，包括以下步骤：在衬底上形成用于粘附层的钛膜，通过在离子注入氧离子之后将钛膜退火形成用于扩散阻挡层的二氧化钛膜 钛膜的表面区域，以将表面区域中的钛变为二氧化钛，并在二氧化钛膜上形成高介电常数电容器。

公开(公告)号：US6080617A

公开(公告)日：2000-06-27

申请号：US950920

申请日：1997-10-15

申请人： Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Shinitirou Hayashi ,  Tooru Nasu ,  Koichi Arita ,  Atsuo Inoue ,  Akihiro Matsuda ,  Masaki Kibe ,  Tatsuo Ootsuki

发明人： Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Shinitirou Hayashi ,  Tooru Nasu ,  Koichi Arita ,  Atsuo Inoue ,  Akihiro Matsuda ,  Masaki Kibe ,  Tatsuo Ootsuki

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/06 ,  H01L27/115 ,  H01L29/92

CPC分类号： H01L27/11502 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/1085 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/55

摘要： A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.

摘要翻译： 一种包括集成电路和电容器的半导体器件。 在该电容器中，在层间绝缘膜上形成独立于集成电路的底电极，电介质膜和顶电极，并且顶电极和底电极通过在保护膜中开口的接触孔与金属互连连接 用于保护电容器的表面。 在这种结构中，顶部电极或底部电极与集成电路的偏置线连接，另一个连接到接地线，使得可以减少外部发射而不必将电容器连接到外部。

公开(公告)号：US6046490A

公开(公告)日：2000-04-04

申请号：US132023

申请日：1998-08-10

申请人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Uemoto ,  Yoshihisa Nagano ,  Akihiro Matsuda

发明人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Uemoto ,  Yoshihisa Nagano ,  Akihiro Matsuda

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L29/40

CPC分类号： H01L28/55 ,  H01L21/76895

摘要： A semiconductor device is provided with a multilayered interconnection and a capacitor dielectric element, in which the transistor in the device has a non-degraded characteristics and the degradation of the capacitor dielectric element is suppressed. The semiconductor device has wiring layers connecting to one another through contact holes in insulating layers. One of the insulating layers is formed so as to cover at least a part of the area above the transistor and so as not to cover the area above the capacitor dielectric element. Hydrogen generated by heat-treating the insulating layer is supplied to the transistor to recover the damage in it, while hydrogen is suppressed from arriving at the capacitor element so that the capacitor dielectric element does not degrade.

摘要翻译： 半导体器件设置有多层互连和电容器介质元件，其中器件中的晶体管具有非劣化特性，并且抑制了电容器介质元件的劣化。 半导体器件具有通过绝缘层中的接触孔彼此连接的布线层。 绝缘层之一形成为覆盖晶体管上方的区域的至少一部分，并且不覆盖电容器介质元件上方的区域。 通过热处理绝缘层产生的氢气被提供给晶体管以恢复其中的损坏，同时抑制氢气到达电容器元件，使得电容器介质元件不劣化。

公开(公告)号：US08405126B2

公开(公告)日：2013-03-26

申请号：US13196512

申请日：2011-08-02

申请人： Daisuke Shibata ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke Shibata ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L29/778

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

摘要翻译： 半导体器件包括形成在衬底上的半导体层堆叠，形成在半导体层堆叠上的第一欧姆电极和第二欧姆电极，并且彼此间隔开，形成在第一欧姆电极和第二欧姆电极之间的第一控制层 第二欧姆电极和形成在第一控制层上的第一栅电极。 第一控制层包括下层，形成在下层上的中间层，并且具有比下层更低的杂质浓度，以及形成在中间层上的上层，并且具有比中间层更高的杂质浓度 层。

公开(公告)号：US20110284928A1

公开(公告)日：2011-11-24

申请号：US13196512

申请日：2011-08-02

申请人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L29/778 ,  H01L27/06

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

摘要翻译： 半导体器件包括形成在衬底上的半导体层堆叠，形成在半导体层堆叠上的第一欧姆电极和第二欧姆电极，并且彼此间隔开，形成在第一欧姆电极和第二欧姆电极之间的第一控制层 第二欧姆电极和形成在第一控制层上的第一栅电极。 第一控制层包括下层，形成在下层上的中间层，并且具有比下层更低的杂质浓度，以及形成在中间层上的上层，并且具有比中间层更高的杂质浓度 层。

公开(公告)号：US20110193171A1

公开(公告)日：2011-08-11

申请号：US12905801

申请日：2010-10-15

申请人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Ayanori Ikoshi ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Ayanori Ikoshi ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L27/088

CPC分类号： H01L29/7786 ,  H01L27/0266 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/8124 ,  H01L29/861

摘要： A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.

摘要翻译： 半导体器件包括形成在第一元件区上的第一晶体管和包括形成在第二元件区上的第二晶体管的第一保护元件。 第二保护元件欧姆电极连接到第一栅电极，第一保护元件欧姆电极连接到第一欧姆电极，第一保护元件栅电极连接至第一保护元件欧姆电极和 第二保护元件欧姆电极。 第二元件区域的面积小于第一元件区域。

公开(公告)号：US20100213503A1

公开(公告)日：2010-08-26

申请号：US12681567

申请日：2009-07-10

申请人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tatsuo Morita ,  Yasuhiro Uemoto

发明人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tatsuo Morita ,  Yasuhiro Uemoto

IPC分类号： H01L29/747

CPC分类号： H01L27/088 ,  H01L23/481 ,  H01L23/4824 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

摘要翻译： 双向开关包括多个单元电池11，其包括第一欧姆电极15，第一栅极电极17，第二栅极电极18和第二欧姆电极16.第一栅电极15经由第一互连线31电连接到 第一栅极电极焊盘43.第二栅电极18经由第二互连32电连接到第二栅极电极焊盘44.单元电池11包括与第一栅电极焊盘43的布线距离最短的第一栅电极17 包括与第二栅电极焊盘44的互连距离最短的第二栅电极18。

公开(公告)号：US20090166677A1

公开(公告)日：2009-07-02

申请号：US12329939

申请日：2008-12-08

申请人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L21/338 ,  H01L29/812

CPC分类号： H01L29/7783 ,  H01L21/26533 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7781 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device includes: a semiconductor substrate; a diode having a cathode formed on a first surface side of the semiconductor substrate and an anode formed on a second surface side of the semiconductor substrate; and a transistor formed over the semiconductor substrate. The transistor includes a semiconductor layer laminate formed over the semiconductor substrate, a source electrode and a drain electrode that are formed spaced apart from each other over the semiconductor layer laminate, and a gate electrode formed between the source electrode and the drain electrode. The source electrode is electrically connected to the anode, and the drain electrode is electrically connected to the cathode.

摘要翻译： 半导体器件包括：半导体衬底; 具有形成在半导体衬底的第一表面侧的阴极和形成在半导体衬底的第二表面侧上的阳极的二极管; 以及形成在半导体衬底上的晶体管。 晶体管包括形成在半导体衬底上的半导体层叠层，在半导体层叠层上彼此隔开形成的源电极和漏极，以及形成在源电极和漏电极之间的栅电极。 源电极与阳极电连接，漏电极与阴极电连接。

公开(公告)号：US07531863B2

公开(公告)日：2009-05-12

申请号：US11270615

申请日：2005-11-10

申请人： Yoshihisa Nagano ,  Yasuhiro Uemoto

发明人： Yoshihisa Nagano ,  Yasuhiro Uemoto

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

公开(公告)号：US06447838B1

公开(公告)日：2002-09-10

申请号：US08543827

申请日：1995-10-16

申请人： Masamichi Azuma ,  Eiji Fujii ,  Yasuhiro Uemoto ,  Shinichiro Hayashi ,  Toru Nasu ,  Yoshihiro Shimada ,  Akihiro Matsuda ,  Tatsuo Otsuki ,  Michael C. Scott ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

发明人： Masamichi Azuma ,  Eiji Fujii ,  Yasuhiro Uemoto ,  Shinichiro Hayashi ,  Toru Nasu ,  Yoshihiro Shimada ,  Akihiro Matsuda ,  Tatsuo Otsuki ,  Michael C. Scott ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

IPC分类号： B05D512

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55 ,  H01L28/65 ,  Y10T29/42

摘要： A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100° C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700° C. for a barrier thickness of about 1000 Å and about 800° C. for a barrier thickness of about 3000 Å. The barrier layer is 800 Å thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.

摘要翻译： 在基板上形成Ti / TiN粘合/阻挡层并退火。 退火步骤在取决于所述阻挡层的厚度的基本阻挡退火温度之上的100℃的良好形态范围内进行。 对于约3000的屏障厚度，对于约1000和约800℃的阻挡层厚度，基底阻挡退火温度为约700℃。 阻挡层厚度为800或更厚。 形成第一电极，随后是BST介电层和第二电极。 还公开了其中TiN阻挡层夹在两层铂之间的底部电极结构。 该工艺和结构也与其他电容器电介质（包括铁电锶钽酸锶）等产生良好的结果。