公开(公告)号：US06548358B2

公开(公告)日：2003-04-15

申请号：US09769494

申请日：2001-01-26

申请人： Kenneth C. Arndt ,  Dureseti Chidambarrao ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl Radens

发明人： Kenneth C. Arndt ,  Dureseti Chidambarrao ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl Radens

IPC分类号： H01L21336

CPC分类号： H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

摘要翻译： 半导体保险丝位于用于连接布线的导体之间。 保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。 导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

公开(公告)号：US06258689B1

公开(公告)日：2001-07-10

申请号：US09626328

申请日：2000-07-26

申请人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

发明人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

IPC分类号： H01L2120

CPC分类号： H01L27/10861 ,  H01L29/66181

摘要： Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

摘要翻译： 使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。 本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。

公开(公告)号：US6013937A

公开(公告)日：2000-01-11

申请号：US938196

申请日：1997-09-26

申请人： Jochen Beintner ,  Ulrike Gruening ,  Carl Radens

发明人： Jochen Beintner ,  Ulrike Gruening ,  Carl Radens

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/00 ,  H01L21/336 ,  H01L21/469 ,  H01L29/06

CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/763 ,  H01L27/10867 ,  Y10S438/97

摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

摘要翻译： 设置在半导体衬底102上的衬垫层和布置在焊盘层内的缓冲层108，使得衬垫层被分为缓冲层下面的介电层106和缓冲层上方的掩模层110。 在半导体芯片上形成具有均匀平坦度和厚度的层的方法包括以下步骤：提供具有形成在其上的热垫106的衬底，在热衬垫上形成电介质层106，在电介质层上形成缓冲层108，其中， 缓冲层由与电介质层不同的材料制成，并在缓冲层上形成掩模层110，其中缓冲层由与掩模层不同的材料制成。

公开(公告)号：US08680577B2

公开(公告)日：2014-03-25

申请号：US13494965

申请日：2012-06-12

申请人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/7781

摘要： A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

摘要翻译： 一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。 沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

公开(公告)号：US20120183743A1

公开(公告)日：2012-07-19

申请号：US13432036

申请日：2012-03-28

申请人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

发明人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

IPC分类号： B32B3/30

CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

公开(公告)号：US20120183736A1

公开(公告)日：2012-07-19

申请号：US13430177

申请日：2012-03-26

申请人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

发明人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

IPC分类号： B32B3/10 ,  B32B3/30

CPC分类号： H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

公开(公告)号：US08024012B2

公开(公告)日：2011-09-20

申请号：US12137185

申请日：2008-06-11

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

IPC分类号： H04B1/38 ,  H04B1/16

CPC分类号： H02J50/20 ,  H02J7/025 ,  H02J17/00

摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

摘要翻译： 一种用于无线网络设备智能电源管理的系统和方法。 该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。 电池通过嵌入在无线设备内部的射频收集单元进行充电。 智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。 第一个适配器设置为数据通信，而第二个适配器用于传输电源。 此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

公开(公告)号：US08009453B2

公开(公告)日：2011-08-30

申请号：US12136089

申请日：2008-06-10

申请人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： G11C19/08 ,  G11C19/38

CPC分类号： G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.

摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括其中具有收缩部的写入线，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续点的位置对应的点处。

公开(公告)号：US20110037143A1

公开(公告)日：2011-02-17

申请号：US12539105

申请日：2009-08-11

申请人： Kevin S. Petrarca ,  Matthew Angyal ,  Lawrence A. Clevenger ,  Carl Radens ,  Brian C. Sapp

发明人： Kevin S. Petrarca ,  Matthew Angyal ,  Lawrence A. Clevenger ,  Carl Radens ,  Brian C. Sapp

IPC分类号： H01L29/92 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/5222 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TV to other BEOL interconnects.

摘要翻译： 线的后端（BEOL）的铝横向互连用于在形成于硅衬底中的半导体芯片中限定穿硅通孔的x和y尺寸。 TSV包括形成在基板的表面上的一个或多个铝环，以及基板中的深沟槽，其直径由铝环的直径决定。 环也可以设置有可以形成电容器的导电带。 带子也可用于提供电视与其他BEOL互连的连接。

公开(公告)号：US07851321B2

公开(公告)日：2010-12-14

申请号：US12348707

申请日：2009-01-05

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/20

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。