公开(公告)号：US06236103B1

公开(公告)日：2001-05-22

申请号：US09283828

申请日：1999-03-31

申请人： Kerry Bernstein ,  Robert M. Geffken ,  Wilbur D. Pricer ,  Anthony K. Stamper ,  Steven H. Voldman

发明人： Kerry Bernstein ,  Robert M. Geffken ,  Wilbur D. Pricer ,  Anthony K. Stamper ,  Steven H. Voldman

IPC分类号： H01L2900

CPC分类号： H01L28/40 ,  H01L23/3672 ,  H01L23/3735 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.

摘要翻译： 一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。 这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物 导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。 去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。 因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

公开(公告)号：US06232639B1

公开(公告)日：2001-05-15

申请号：US09107900

申请日：1998-06-30

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。 优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。 植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。 这降低了CMOS器件闭锁的倾向。 优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。 此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

公开(公告)号：US06187617B1

公开(公告)日：2001-02-13

申请号：US09363558

申请日：1999-07-29

申请人： Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Steven H. Voldman

发明人： Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Steven H. Voldman

IPC分类号： H01L21336

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/456

摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.

摘要翻译： 在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。 然后将钛沉积在半导体衬底（10）上。 半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅 该基板在高电阻率C49晶相中形成硅化钛。 在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。

公开(公告)号：US6166420A

公开(公告)日：2000-12-26

申请号：US526369

申请日：2000-03-16

申请人： Robert J. Gauthier, Jr. ,  Dominic J. Schepis ,  Steven H. Voldman

发明人： Robert J. Gauthier, Jr. ,  Dominic J. Schepis ,  Steven H. Voldman

IPC分类号： H01L27/04 ,  H01L21/762 ,  H01L21/822 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00 ,  H01L23/58

CPC分类号： H01L21/7624

摘要： A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.

摘要翻译： 用于形成集成电路晶片的方法和结构包括形成具有第一和第二部分的衬底，在衬底上沉积第一绝缘体，图案化第一绝缘体，使得第一绝缘体仅保留在第一部分之上，在衬底上沉积第二绝缘体 （第一绝缘体具有与第二绝缘体不同的散热特性），抛光第二绝缘体以形成平坦表面，并且在第一绝缘体和第二绝缘体上附着硅膜。

公开(公告)号：US6100143A

公开(公告)日：2000-08-08

申请号：US267239

申请日：1999-03-12

申请人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/6659 ,  H01L21/28105 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/4238 ,  H01L29/4983 ,  Y10S438/919

摘要： A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance. The structure has improved edge dielectric breakdown and lower MOSFET gate-induced drain leakage (GIDL). This structure is intended for analog applications, mixed voltage tolerant circuits and electrostatic (ESD) networks.

摘要翻译： 具有减小的拐角设备问题的场效应晶体管包括形成在衬底中的源极和漏极区域，源极和漏极区域之间的沟道区域，邻近源极，沟道和漏极区域的衬底中的隔离区域; 以及在沟道区域上具有栅极掺杂剂并由栅极电介质分离的栅极。 隔离区域定义了通道与隔离区域之间的接口的拐角区域。 栅极包括耗尽栅极掺杂剂的区域，并且至少与沟道区域和隔离区域重叠，使得栅极导体层的耗尽部分之下的沟道拐角区域的电压阈值与角区域之间的沟道区域相比增加 。 MOSFET栅极“拐角”上掺杂浓度降低的场效应晶体管具有改善的边缘电压容差。 该结构具有改善的边缘电介质击穿和较低的MOSFET栅极引起的漏极泄漏（GIDL）。 该结构适用于模拟应用，混合耐压电路和静电（ESD）网络。

公开(公告)号：US6096584A

公开(公告)日：2000-08-01

申请号：US38936

申请日：1998-03-12

申请人： John J. Ellis-Monaghan ,  Steven H. Voldman

发明人： John J. Ellis-Monaghan ,  Steven H. Voldman

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L27/0251 ,  H01L21/84 ,  H01L27/1203

摘要： Silicon is formed at selected locations on a silicon-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.

摘要翻译： 在制造所选择的电子部件（包括电阻器，电容器和二极管）期间，在硅绝缘体（SOI）衬底上的选定位置处形成硅。 使用图案化的可移除掩模限定硅位置，并且可以通过沉积或生长来施加硅，并且可以采用多晶硅或晶体硅的形式。 通过在选定区域中具有厚的双层硅，显着改善了SOI器件的静电放电（ESD）特性。

公开(公告)号：US06071803A

公开(公告)日：2000-06-06

申请号：US192586

申请日：1998-11-17

申请人： Matthew J. Rutten ,  Steven H. Voldman

发明人： Matthew J. Rutten ,  Steven H. Voldman

IPC分类号： H01L21/768 ,  H01L21/336 ,  H01L21/84 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00 ,  H01L21/4763

CPC分类号： H01L21/743 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002

摘要： Electrically conductive studs are employed to interconnect bulk active devices and SOI devices in a semiconductor device. Also provided is a method for fabricating such devices.

摘要翻译： 导电柱用于在半导体器件中互连体积有源器件和SOI器件。 还提供了一种用于制造这种装置的方法。

公开(公告)号：US6033949A

公开(公告)日：2000-03-07

申请号：US107813

申请日：1998-06-30

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。 优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。 植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。 这降低了CMOS器件闭锁的倾向。 优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。 此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

公开(公告)号：US5882967A

公开(公告)日：1999-03-16

申请号：US852850

申请日：1997-05-07

申请人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/866 ,  H01L21/8234

CPC分类号： H01L27/0255 ,  H01L21/8238

摘要： According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.

摘要翻译： 根据本发明，公开了一种用于CMOS处理中的埋二极管形成的改进方法。 使用混合光刻胶工艺，使用两步光刻掩模工艺创建自对准齐纳二极管。 由于本发明公开的方法仅使用p阱和n-阱掩模来产生齐纳二极管，所以减小了光刻对准问题，并且可以在亚微米级产生齐纳二极管。

公开(公告)号：US5637912A

公开(公告)日：1997-06-10

申请号：US653752

申请日：1996-05-31

申请人： Martha A. C. Cockerill ,  John G. Maltabes ,  Loretta J. O'Connor ,  Steven H. Voldman

发明人： Martha A. C. Cockerill ,  John G. Maltabes ,  Loretta J. O'Connor ,  Steven H. Voldman

IPC分类号： H01L25/00 ,  H01L21/66 ,  H01L21/98 ,  H01L25/065 ,  H01L27/00

CPC分类号： H01L25/50 ,  H01L22/20 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002

摘要： A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

摘要翻译： 一种制造方法和合成的单片电子模块，其包括多个堆叠的平面扩展阵列的集成电路芯片。 该制造方法包括将集成电路芯片的晶片切割成多个集成电路芯片阵列。 然后将集成电路芯片的阵列堆叠以形成电子模块。 金属化图案可以沉积在电子模块的基本平坦的表面上，并且用于互连其中包含的各种集成电路芯片阵列。 阐述制造方法和结果多芯片封装的具体细节。