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179 条记录 (耗时 0.051 秒)

    SEMICONDUCTOR MEMORY DEVICE
    91.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20080181026A1

    公开(公告)日：2008-07-31

    申请号：US11963831

    申请日：2007-12-22

    申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    IPC分类号： G11C7/08

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

    摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

    摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

    Semiconductor Device
    92.
    发明申请
    Semiconductor Device 失效
    半导体器件

    公开(公告)号：US20080094922A1

    公开(公告)日：2008-04-24

    申请号：US11924353

    申请日：2007-10-25

    申请人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

    发明人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1027 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/028 ,  G11C2207/002

    摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

    摘要翻译： 提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。 在每个子放大器SAMP中设置有能够根据读使能信号RD1，RD2设定两种电流之一的电流控制电路IC。 在定时控制器的控制下，在与脉冲串读取操作中的周期数相对应的定时，生成读使能信号RD 1，RD 2。 电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD 1被设置为较大，而当前控制电路IC中的电流被下一个的RD 2设置得较小时， 随后的突发读取周期。 因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

    Semiconductor memory device
    93.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20070268771A1

    公开(公告)日：2007-11-22

    申请号：US11655945

    申请日：2007-01-22

    申请人： Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C8/10

    CPC分类号： G11C8/12 ,  G11C5/025 ,  G11C5/04 ,  G11C7/18 ,  G11C11/4097 ,  H01L25/0657 ,  H01L27/0207 ,  H01L27/10814 ,  H01L2224/4826 ,  H01L2924/13091 ,  H01L2924/00

    摘要： If memory cell blocks are laid out in a conventional manner to create a memory chip with a capacity of an odd power of 2 by using memory cells whose aspect ratio is 1:2, the chip will take a 1:1 shape and become difficult to enclose in a package of a 1:2 shape. In addition, such conventional layout of memory cell blocks to form the 1:2 shape causes the area of a peripheral circuit region to be limited by the memory blocks, pads to be arranged collectively in the central section of the chip, and wiring to become dense during the enclosure of the chip in the package. In this invention, therefore, four memory blocks, BANK0, BANK1, BANK2, BANK3, BANK3, are constructed into an L shape and then these memory blocks are properly combined and arranged to construct a chip of nearly a 1:2 shape in terms of aspect ratio.

    摘要翻译： 如果通过使用纵横比为1:2的存储单元，以常规方式布置存储单元块以创建具有2的奇数功率的容量的存储芯片，则芯片将采取1：1的形状并变得难以 以1：2的形状包装。 此外，存储单元块的这种传统布局形成1：2形状会导致外围电路区域的区域受到存储块的限制，焊盘将被集中布置在芯片的中心部分中，并且布线成为 密封在芯片封装中的封装。 因此，在本发明中，将四个存储器块BANK0，BANK1，BANK2，BANK3，BANK3构造成L形，然后这些存储块被适当地组合并布置成构成近似1：2形状的芯片 长宽比。

    Information processor
    94.
    发明申请
    Information processor 有权
    信息处理器

    公开(公告)号：US20070226405A1

    公开(公告)日：2007-09-27

    申请号：US11703762

    申请日：2007-02-08

    申请人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

    发明人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0802 ,  G06F2212/2515 ,  G11C29/76 ,  Y02D10/13

    摘要： In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

    摘要翻译： 在包括诸如DRAM等存储器件的信息处理器中，通过降低存储器件的功耗并有效地修复缺陷位，实现了高度可靠的信息处理器。 在包括诸如DRAM的外部存储器的信息处理器中，设置存取时间小于外部存储器的功耗的第二存储器，并且将外部存储器和修复数据的高速缓存数据存储在该第二存储器中 。 对于通过主缓存控制器从中央处理单元给出的输入地址，存储器控制器参考用于高速缓存的标签存储器和用于修复的标签存储器以及当缓存的标签存储器中的一个或两个时，确定命中或未命中 并且用于修复的标签存储器被命中，它访问第二存储器。

    SEMICONDUCTOR MEMORY DEVICE
    96.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20070187736A1

    公开(公告)日：2007-08-16

    申请号：US11737693

    申请日：2007-04-19

    申请人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

    发明人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

    IPC分类号： H01L29/94

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

    摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

    摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

    Semiconductor memory device using vertical-channel transistors
    99.
    发明申请
    Semiconductor memory device using vertical-channel transistors 失效
    半导体存储器件采用垂直沟道晶体管

    公开(公告)号：US20050253143A1

    公开(公告)日：2005-11-17

    申请号：US11168872

    申请日：2005-06-29

    申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

    发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

    IPC分类号： G11C11/41 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/10

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

    摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

    摘要翻译： 本发明提供一种包括多个字线，多个位线以及多个静态存储单元的半导体存储器件，每个静态存储器单元具有第一，第二，第三，第四，第五和第六和第六晶体管。 尽管第一，第二，第三和第四晶体管的每个通道与半导体存储器件的衬底垂直地形成。 形成第五晶体管和第六晶体管的源极或漏极的半导体区域形成与衬底相反的PN结。 根据本发明的另一方面，本发明的SRAM器件具有多个SRAM单元，其中至少一个是在衬底上包括至少四个垂直晶体管的垂直SRAM单元，并且每个垂直晶体管包括源极， 排水管和其间的通道在以大于零度的角度穿入衬底表面的一个对准线对中。

    Semiconductor memory device
    100.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06828612B2

    公开(公告)日：2004-12-07

    申请号：US10388639

    申请日：2003-03-17

    申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    IPC分类号： H01L27108

    CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

    摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

    摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/位方法的DRAM具有采用单交叉6F 2单元的双单元结构，其结构是：存储器单元被布置在对应于位之间的所有交点的位置 线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。 此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。