公开(公告)号：US12183630B2

公开(公告)日：2024-12-31

申请号：US17691085

申请日：2022-03-09

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Chih-Chao Yang ,  Jennifer Church

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

公开(公告)号：US12144263B2

公开(公告)日：2024-11-12

申请号：US17489888

申请日：2021-09-30

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Lili Cheng ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor device, such as an MRAM device, includes a stepped contact within a memory region that has a greater number of different contact structures (i.e., contact structures formed in different fabrication stages) relative to a logic region contact. The stepped contact includes a lower stepped contact and an upper stepped contact. The inclusion of the lower stepped contact allows for a relatively shorter upper stepped contact compared to the logic region contact. The stepped contact may allow the use of a multi-layer encapsulation spacer upon the sidewalls of a memory cell that fill out tight spacing therebetween, which may decrease the propensity of void formation and resulting shorting between neighboring memory cell features.

公开(公告)号：US12133473B2

公开(公告)日：2024-10-29

申请号：US17484453

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor structure comprises a memory device comprising a first electrode, at least one memory element layer disposed on the first electrode, and a second electrode disposed on the at least one memory element layer. An encapsulation layer is disposed around side surfaces of the memory device. The semiconductor structure also comprises a conductive cap layer disposed on a top surface of the encapsulation layer and around a portion of side surfaces of the encapsulation layer. A contact is disposed on the second electrode and extends around the side surfaces of the memory device.

公开(公告)号：US20240312834A1

公开(公告)日：2024-09-19

申请号：US18185481

申请日：2023-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  SON NGUYEN ,  Matthew T. Shoudy ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76843 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A first BEOL layer, including a first and a second signal line, a conformal dielectric surrounding an upper portion of a vertical sidewall of each of the first signal line and the second signal line, an air gap between the first and the second signal line, a vertical side boundary of the air gap is a vertical side surface of the first signal line. Forming a first and a second metal line in a sacrificial material in a first BEOL layer, removing the sacrificial material, forming a conformal dielectric surrounding vertical side surfaces of the first and the second metal line, an air gap between the first and the second metal line exposes an upper horizontal surface of a dielectric layer below the first BEOL layer, growing a dielectric selectively from an upper portion of the conformal dielectric, the air gap remains between the first and the second metal line.

公开(公告)号：US20240206346A1

公开(公告)日：2024-06-20

申请号：US18081960

申请日：2022-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shravana Kumar Katakam ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure, a system, and a method of forming an MRAM structure. The MRAM structure may include a bottom electrode. The bottom electrode may include a diffusion barrier. The bottom electrode may further include a dielectric that surrounds one or more sidewalls of the diffusion barrier. The method may include depositing a first dielectric, where a metal component remains uncovered by the dielectric. The method may further include depositing a diffusion barrier on at least the metal component. The method may further include depositing an electrode layer on the first dielectric and the diffusion barrier, resulting in a bottom electrode comprising the electrode layer, the first dielectric, and the diffusion barrier.

公开(公告)号：US20240099035A1

公开(公告)日：2024-03-21

申请号：US17946147

申请日：2022-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wu-Chang Tsai ,  Ailian Zhao ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01L27/105 ,  H01L23/48

CPC classification number: H01L27/1052 ,  H01L23/481

Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.

公开(公告)号：US11849647B2

公开(公告)日：2023-12-19

申请号：US17249521

申请日：2021-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Yann Mignot ,  Ashim Dutta ,  Tsung-Sheng Kang ,  Wenyu Xu

IPC: H10N50/10 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/80 ,  H10N50/01 ,  H10N50/10

Abstract: A semiconductor structure may include a magnetic tunnel junction layer on top and in electrical contact with a microstud, a hard mask layer on top of the magnetic tunnel junction layer, and a liner positioned along vertical sidewalls of the magnetic tunnel junction layer and vertical sidewalls of the hard mask layer. A top surface of the liner may be below a top surface of the hard mask layer. The semiconductor structure may include a spacer on top of the liner. The liner may separate the spacer from the magnetic tunnel junction layer and the hard mask layer. The semiconductor structure may include a first metal layer below and in electrical contact with the microstud and a second metal layer above the hard mask layer. A bottom portion of the second metal layer may surround a top portion of the hard mask layer.

公开(公告)号：US11751492B2

公开(公告)日：2023-09-05

申请号：US17484649

申请日：2021-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dexin Kong ,  Ashim Dutta ,  Ekmini Anuja De Silva ,  Daniel Schmidt

IPC: G11C13/00 ,  H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N70/068 ,  H10B61/00 ,  H10B63/80 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N70/023 ,  H10N70/063 ,  H10N70/066 ,  H10N70/841

Abstract: A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.

公开(公告)号：US20230180618A1

公开(公告)日：2023-06-08

申请号：US17542696

申请日：2021-12-06

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L43/08 ,  G11C11/161 ,  H01L43/10 ,  H01L43/02 ,  H01L27/222

Abstract: Embodiments of the invention include a subtractive top via as a bottom electrode contact for an embedded memory structure. Forming the bottom electrode contact includes depositing a conductive material on an underlayer and etching the conductive material to form an extended via and a conductive pad as an integral unit. The extended via extends from the conductive pad such that the extended via is adjacent to a memory structure, the extended via being formed as a first contact for the memory structure.

公开(公告)号：US20230178431A1

公开(公告)日：2023-06-08

申请号：US17643395

申请日：2021-12-08

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Ruilong Xie

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76885 ,  H01L21/76837 ,  H01L23/5226 ,  H01L23/53257

Abstract: A first metal layer is deposited on a substrate. The first metal layer is etched to form one or more metal lines and expose portions of the substrate. A second metal layer is deposited on the exposed portions of the substrate between the one or more metal lines. The first metal layer is patterned to form one or more vertical vias. A dielectric layer is deposited on the exposed portions of the substrate between an exposed sidewalls of the first metal layer and an exposed sidewalls of the second metal layer.