公开(公告)号：US20150372127A1

公开(公告)日：2015-12-24

申请号：US14524279

申请日：2014-10-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo CHENG ,  Ryan O. JUNG ,  Fee Li LIE ,  Jeffrey C. SHEARER ,  John R. SPORRE ,  Sean TEEHAN

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/04

CPC classification number: H01L21/28132 ,  H01L21/32139 ,  H01L27/0886 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.

公开(公告)号：US20150021690A1

公开(公告)日：2015-01-22

申请号：US13945415

申请日：2013-07-18

Applicant: International Business Machines Corporation ,  Global Foundries Inc.

Inventor： Ajey Poovannummoottil JACOB ,  Kangguo CHENG ,  Bruce B. DORIS ,  Nicolas LOUBET ,  Prasanna KHARE ,  Ramachandra DIVAKARUNI

IPC: H01L21/02 ,  H01L27/088

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。

公开(公告)号：US20140295647A1

公开(公告)日：2014-10-02

申请号：US14054152

申请日：2013-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A computer program storage product includes instructions for forming a fin field-effect-transistor. The instructions are configured to perform a method. The method includes implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.

Abstract translation: 计算机程序存储产品包括用于形成鳍状场效应晶体管的指令。 指令被配置为执行一种方法。 该方法包括将掺杂剂注入腔内的半导体衬底的暴露部分。 空腔形成在半导体衬底上的电介质层中。 空腔将半导体衬底的部分暴露在空腔内。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。 空腔的高度限定外延生长的半导体的高度。

公开(公告)号：US20140264496A1

公开(公告)日：2014-09-18

申请号：US14031111

申请日：2013-09-19

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/78

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785

Abstract: A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of sidewalls of the at least one semiconducting fin and the gate stack. The stress liner imparts stress to at least a source region, a drain region, and a channel region of the at least one semiconducting fin. The channel region is located in at least one semiconducting fin beneath the gate stack.

Abstract translation: 具有增强应变的非平面半导体包括衬底和形成在衬底的表面上的至少一个半导体鳍。 栅极堆叠形成在至少一个半导体鳍片的一部分上。 在至少一个半导体翅片和栅极叠层的多个侧壁中的至少每一个上形成应力衬垫。 应力衬垫向至少一个半导体鳍片的源极区域，漏极区域和沟道区域施加应力。 沟道区域位于栅堆叠下方的至少一个半导体鳍片中。

公开(公告)号：US20130210206A1

公开(公告)日：2013-08-15

申请号：US13852428

申请日：2013-03-28

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Balasubramanian S. HARAN ,  Shom PONOTH ,  Theodorus E. STANDAERT ,  Tenko YAMASHITA

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

Abstract: A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

公开(公告)号：US20230093101A1

公开(公告)日：2023-03-23

申请号：US17481706

申请日：2021-09-22

Applicant: International Business Machines Corporation

Inventor： Ruilong XIE ,  Brent ANDERSON ,  Albert M. YOUNG ,  Kangguo CHENG ,  Julien FROUGIER ,  Balasubramanian PRANATHARTHIHARAN ,  Roy R. YU ,  Takeshi NOGAMI

IPC: H01L29/40 ,  H01L29/165 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522 ,  H01L21/762 ,  H01L21/84

Abstract: A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

公开(公告)号：US20210288468A1

公开(公告)日：2021-09-16

申请号：US16819250

申请日：2020-03-16

Applicant: International Business Machines Corporation

Inventor： Julien FROUGIER ,  Kangguo CHENG ,  Ruilong Xie ,  Chanro PARK

IPC: H01S5/10 ,  H01S5/062

Abstract: A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor laser and a BRS operating as a reversible switch. The BRS operates in a high resistive state in which a semiconductor laser is below a lasing threshold and emitting in a reduced spontaneous emission regime, and a low resistive state in which a semiconductor laser is above or equal to a lasing threshold and emitting in a stimulated emission regime. The BRS operating as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using insulator-to-metal transition (IMT) materials or is formed using threshold-switching selectors (TSS).

公开(公告)号：US20200273704A1

公开(公告)日：2020-08-27

申请号：US16287107

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Chanro PARK ,  Ruilong Xie ,  Kangguo CHENG ,  Choonghyun LEE

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/308 ,  G03F7/20

Abstract: A photolithography patterning stack and method for forming the same. The stack includes a plurality of patterned silicon oxide lines. A plurality of patterned silicon germanium lines each underlie and contact one patterned silicon oxide line of the plurality of patterned silicon oxide lines. The photolithography patterning stack further comprises a plurality of layers underlying the plurality of patterning silicon germanium lines. The method includes patterning at least a photoresist layer of a photolithographic patterning stack. The patterning exposing portions of a silicon germanium layer of the photolithographic patterning stack. A germanium oxide layer is formed in contact with the patterned photoresist layer and the portions of the silicon germanium layer. A plurality of silicon oxide layers is formed from the germanium oxide layer. Each of the silicon oxide layer is in contact with one of the portions of the silicon germanium layer.

公开(公告)号：US20200266288A1

公开(公告)日：2020-08-20

申请号：US16581867

申请日：2019-09-25

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Ruilong Xie ,  Chanro PARK

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a semiconductor fin and a liner in contact with end portions of the semiconductor fin. A first source/drain contacts the liner and sidewalls of the semiconductor fin. A gate structure is in contact with and surrounds the semiconductor fin. A second source/drain is formed above the first source/drain. The method includes forming, on a substrate, at least one semiconductor fin having a first spacer in contact with an upper portion of the semiconductor fin, and a second spacer in contact with the first spacer and a lower portion of the semiconductor fin. The semiconductor fin is patterned into a plurality of semiconductor fins. A liner is formed on exposed end portions of each semiconductor fin of the plurality of semiconductor fins.

公开(公告)号：US20200027967A1

公开(公告)日：2020-01-23

申请号：US16587340

申请日：2019-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L29/49 ,  H01L23/485 ,  H01L29/417 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.