公开(公告)号：US20230344871A1

公开(公告)日：2023-10-26

申请号：US18216412

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Francesc Guim Bernat ,  Sunil Cheruvu ,  Kshitij Arun Doshi ,  Marcos E. Carranza

IPC: H04L9/40 ,  H04L67/60

CPC classification number: H04L63/20 ,  H04L67/60

Abstract: Software and other electronic services are increasingly being executed in cloud computing environments. Edge computing environments may be used to bridge the gap between cloud computing environments and end-user software and electronic devices, and may implement Functions-as-a-Service (FaaS). FaaS may be used to create flavors of particular services, a chain of related functions that implements all or a portion of a FaaS edge workflow or workload. A FaaS Temporal Software-Defined Wide-Area Network (SD-WAN) may be used to receive a computing request and decompose the computing request into several FaaS flavors, enable dynamic creation of SD-WANs for each FaaS flavor, execute the FaaS flavors in their respective SD-WAN, return a result, and destroy the SD-WANs. The FaaS Temporal SD-WAN expands upon current edge systems by allowing low-latency creation of SD-WAN virtual networks bound to a set of function instances that are created to a execute a particular service request.

公开(公告)号：US11792280B2

公开(公告)日：2023-10-17

申请号：US18067097

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L67/51 ,  H04L67/562 ,  H04L41/5009 ,  H04L9/32 ,  H04L9/00

CPC classification number: H04L67/51 ,  H04L9/3278 ,  H04L41/5009 ,  H04L67/562 ,  H04L9/50

Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to: obtain, by a microservice of a service hosted in a datacenter, provisioned credentials for the microservice based on an attestation protocol; generate, for a task performed by the microservice, provenance metadata for the task, the provenance metadata including identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and operating state of a sidecar of the microservice during the task; encrypt the provenance metadata with the provisioned credentials for the microservice; and record the encrypted provenance metadata in a local blockchain of provenance metadata maintained for the hardware resource executing the task and the microservice.

公开(公告)号：US20230273839A1

公开(公告)日：2023-08-31

申请号：US18311047

申请日：2023-05-02

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Arun Hodigere ,  John J. Browne ,  Henning Schroeder ,  Kshitij Arun Doshi

IPC: G06F9/50 ,  G06F1/20

CPC classification number: G06F9/5094 ,  G06F1/206

Abstract: An example apparatus to balance and coordinate power and cooling includes memory; machine-readable instructions; and programmable circuitry to execute the machine-readable instructions to: determine a first service level objective based on a service level agreement and resource data; modify the first service level objective to generate a second service level objective based on the first service level objective and an ambient temperature prediction; determine a resource budget based on a resource usage prediction, the resource budget to identify available resources at a given time; and cause an allocation of cooling resources and power resources for a compute component based on the second service level objective and the resource budget.

公开(公告)号：US20230267004A1

公开(公告)日：2023-08-24

申请号：US18141681

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Ned M. Smith ,  Francesc Guim Bernat ,  Timothy Verrall

IPC: G06F9/50 ,  H04L9/40 ,  H04L9/08 ,  H04L9/06 ,  H04L41/0893 ,  H04L41/5009 ,  H04L41/5025 ,  H04L43/08 ,  H04L67/1008 ,  G06F9/54 ,  G06F21/60 ,  H04L41/0896 ,  H04L41/142 ,  H04L41/5051 ,  H04L67/141 ,  H04L41/14 ,  H04L47/70 ,  H04L67/12 ,  G06F8/41 ,  G06F9/445 ,  G06F11/34 ,  G06F16/18 ,  H04L9/00

CPC classification number: G06F9/5016 ,  H04L63/0428 ,  H04L63/0407 ,  H04L63/20 ,  H04L9/0822 ,  H04L9/0637 ,  H04L9/0825 ,  H04L9/0866 ,  H04L41/0893 ,  H04L41/5009 ,  H04L41/5025 ,  H04L43/08 ,  H04L63/1408 ,  H04L67/1008 ,  G06F9/544 ,  G06F21/602 ,  H04L41/0896 ,  H04L41/142 ,  H04L41/5051 ,  H04L67/141 ,  H04L41/145 ,  H04L47/822 ,  H04L67/12 ,  G06F8/443 ,  G06F9/44594 ,  G06F9/505 ,  G06F11/3433 ,  G06F9/5072 ,  G06F16/1865 ,  H04L9/008 ,  G06F9/5077 ,  G06F12/1408

Abstract: Various approaches for implementing multi-tenant data protection are described. In an edge computing system deployment, a system includes memory and processing circuitry coupled to the memory. The processing circuitry is configured to obtain a workflow execution plan that includes workload metadata defining a plurality of workloads associated with a plurality of edge service instances executing respectively on one or more edge computing devices. The workload metadata is translated to obtain workload configuration information for the plurality of workloads. The workload configuration information identifies a plurality of memory access configurations and service authorizations identifying at least one edge service instance authorized to access one or more of the memory access configurations. The memory is partitioned into a plurality of shared memory regions using the memory access configurations. A memory access request for accessing one of the shared memory regions is processed based on the service authorizations.

公开(公告)号：US11736942B2

公开(公告)日：2023-08-22

申请号：US17076452

申请日：2020-10-21

Applicant: Intel Corporation

Inventor： Alexander Bachmutsky ,  Dario Sabella ,  Francesc Guim Bernat ,  John J. Browne ,  Kapil Sood ,  Kshitij Arun Doshi ,  Mats Gustav Agerstam ,  Ned M. Smith ,  Rajesh Poornachandran ,  Tarun Viswanathan

IPC: H04W12/08 ,  H04W76/10 ,  H04W28/02 ,  G06F9/455 ,  H04W4/46 ,  H04L67/10 ,  H04W12/42 ,  H04W12/60 ,  H04W12/06 ,  H04W84/12

CPC classification number: H04W12/08 ,  G06F9/45558 ,  H04L67/10 ,  H04W4/46 ,  H04W12/068 ,  H04W12/42 ,  H04W12/66 ,  H04W28/02 ,  H04W76/10 ,  H04W84/12

Abstract: A service coordinating entity device includes communications circuitry to communicate with a first access network, processing circuitry, and a memory device. The processing circuitry is to perform operations to, in response to a request for establishing a connection with a user equipment (UE) in a second access network, retrieve a first Trusted Level Agreement (TLA) including trust attributes associated with the first access network. One or more exchanges of the trust attributes of the first TLA and trust attributes of a second TLA associated with the second access network are performed using a computing service executing on the service coordinating entity. A common TLA with trust attributes associated with communications between the first and second access networks is generated based on the exchanges. Data traffic is routed from the first access network to the UE in the second access network based on the trust attributes of the common TLA.

公开(公告)号：US20230244560A1

公开(公告)日：2023-08-03

申请号：US18192575

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Amruta Misra ,  Arun Hodigere ,  Kshitij Arun Doshi ,  John J. Browne

IPC: G06F11/07 ,  G06F1/20 ,  G06Q10/20 ,  G06F9/48

CPC classification number: G06F11/076 ,  G06F1/20 ,  G06Q10/20 ,  G06F9/4856 ,  G06F11/0709

Abstract: Methods and apparatus for maintaining the cooling systems of distributed compute systems are disclosed. An example apparatus disclosed herein includes memory, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to determine a health of a server, determine a threshold based on a workload service level agreement associated with the server, and in response to determining the health does not a satisfy the threshold, throttle a workload on the server.

公开(公告)号：US20230222363A1

公开(公告)日：2023-07-13

申请号：US18091874

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Suraj Prabhakaran ,  Kshitij Arun Doshi ,  Da-Ming Chiang ,  Joe Cahill

IPC: G06N5/04

CPC classification number: G06N5/04

Abstract: Various systems and methods of initiating and performing contextualized AI inferencing, are described herein. In an example, operations performed with a gateway computing device to invoke an inferencing model include receiving and processing a request for an inferencing operation, selecting an implementation of the inferencing model on a remote service based on a model specification and contextual data from the edge device, and executing the selected implementation of the inferencing model, such that results from the inferencing model are provided back to the edge device. Also in an example, operations performed with an edge computing device to request an inferencing model include collecting contextual data, generating an inferencing request, transmitting the inference request to a gateway device, and receiving and processing the results of execution. Further techniques for implementing a registration of the inference model, and invoking particular variants of an inference model, are also described.

公开(公告)号：US20230198959A1

公开(公告)日：2023-06-22

申请号：US17556671

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Cesar Martinez-Spessot ,  Marcos Carranza ,  Lakshmi Talluru ,  Mateo Guzman ,  Francesc Guim Bernat ,  Karthik Kumar ,  Rajesh Poornachandran ,  Kshitij Arun Doshi

IPC: H04L9/40 ,  G06F9/54

CPC classification number: H04L63/0428 ,  G06F9/547

Abstract: Embodiments described herein are generally directed to a transparent and adaptable mechanism for performing secure application communications through sidecars. In an example, a set of security features is discovered by a first sidecar of a first microservice of multiple microservices of an application. The set of security features are associated with a device of multiple devices of a set of one or more host systems on which the first microservice is running. Information regarding the set of discovered security features is made available to the other microservices by the first sidecar by sharing the information with a discovery service accessible to all of the microservices. A configuration of a communication channel through which a message is to be transmitted from a second microservice to the first microservice is determined by a second sidecar of the second microservice by issuing a request to the discovery service regarding the first microservice.

公开(公告)号：US20230198875A1

公开(公告)日：2023-06-22

申请号：US17556051

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L43/0817 ,  H04L43/0894 ,  H04L43/0864 ,  H04L41/5009 ,  G06N20/00

CPC classification number: H04L43/0817 ,  G06N20/00 ,  H04L41/5009 ,  H04L43/0864 ,  H04L43/0894

Abstract: An apparatus to facilitate at-scale telemetry using interactive matrix for deterministic microservices performance is disclosed. The apparatus includes one or more processors to: receive user input comprising an objective or task corresponding to scheduling a microservice for a service, wherein the objective or task may include QoS, SLO, ML feedback; identify interaction matrix components in an interaction matrix that match the objective or tasks for the microservice; identify knowledgebase components in knowledgebase that match the objective or tasks for the microservice; and determine a scheduling operation for the microservice, the scheduling operation to deploy the microservice in a configuration that is in accordance with the objective or task, wherein the configuration comprises a set of hardware devices and microservice interaction points determined based on the interaction matrix components and the knowledgebase components.

公开(公告)号：US11669368B2

公开(公告)日：2023-06-06

申请号：US16723358

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Ned M. Smith ,  Francesc Guim Bernat ,  Timothy Verrall

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/54 ,  H04L9/40 ,  H04L9/08 ,  H04L9/06 ,  H04L41/0893 ,  H04L41/5009 ,  H04L41/5025 ,  H04L43/08 ,  H04L67/1008 ,  G06F21/60 ,  H04L41/0896 ,  H04L41/142 ,  H04L41/5051 ,  H04L67/141 ,  H04L41/14 ,  H04L47/70 ,  H04L67/12 ,  G06F8/41 ,  G06F9/445 ,  G06F11/34 ,  G06F16/18 ,  H04L9/00 ,  G06F12/14 ,  G06F9/455 ,  G06F16/23 ,  G06F11/10 ,  H04L9/32 ,  H04L67/10 ,  G16Y40/10 ,  G06F9/48

CPC classification number: G06F9/5016 ,  G06F8/443 ,  G06F9/44594 ,  G06F9/505 ,  G06F9/5072 ,  G06F9/5077 ,  G06F9/544 ,  G06F11/3433 ,  G06F16/1865 ,  G06F21/602 ,  H04L9/008 ,  H04L9/0637 ,  H04L9/0822 ,  H04L9/0825 ,  H04L9/0866 ,  H04L41/0893 ,  H04L41/0896 ,  H04L41/142 ,  H04L41/145 ,  H04L41/5009 ,  H04L41/5025 ,  H04L41/5051 ,  H04L43/08 ,  H04L47/822 ,  H04L63/0407 ,  H04L63/0428 ,  H04L63/1408 ,  H04L63/20 ,  H04L67/1008 ,  H04L67/12 ,  H04L67/141 ,  G06F9/3836 ,  G06F9/45533 ,  G06F9/4881 ,  G06F9/5038 ,  G06F11/1004 ,  G06F12/1408 ,  G06F16/2322 ,  G06F2209/509 ,  G16Y40/10 ,  H04L9/3297 ,  H04L67/10

Abstract: In an edge computing system deployment, a system includes memory and processing circuitry coupled to the memory. The processing circuitry is configured to obtain a workflow execution plan that includes workload metadata defining a plurality of workloads associated with a plurality of edge service instances executing respectively on one or more edge computing devices. The workload metadata is translated to obtain workload configuration information for the plurality of workloads. The workload configuration information identifies a plurality of memory access configurations and service authorizations identifying at least one edge service instance authorized to access one or more of the memory access configurations. The memory is partitioned into a plurality of shared memory regions using the memory access configurations. A memory access request for accessing one of the shared memory regions is processed based on the service authorizations.