公开(公告)号：US07211489B1

公开(公告)日：2007-05-01

申请号：US10934378

申请日：2004-09-07

申请人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

发明人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/268 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

摘要： The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel effects are prevented by the use of highly localized halo implant regions formed in the device channel. Highly localized halo implant regions are formed by a tilt pre-amorphization implant and a laser thermal anneal of the halo implant region.

摘要翻译： 本发明能够制造改进的高可靠性，高密度的半导体器件。 本发明通过减小诸如栅极沟道长度的半导体器件结构的尺寸来提供高密度半导体器件。 通过使用在器件通道中形成的高度局部化的注入区来防止短沟道效应。 通过倾斜预非晶化植入和晕圈植入区域的激光热退火形成高度局部化的注入区域。

公开(公告)号：US07170084B1

公开(公告)日：2007-01-30

申请号：US10872707

申请日：2004-06-21

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66477 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

摘要翻译： 在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。 形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。 第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。 通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

公开(公告)号：US07033893B1

公开(公告)日：2006-04-25

申请号：US10827432

申请日：2004-04-20

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823807

摘要： CMOS devices with balanced drive currents are formed with a PMOS transistor based on SiGe and a deposited high-k gate dielectric. Embodiments including forming a composite substrate comprising a layer of strained Si on a layer of SiGe, forming isolation regions defining a PMOS region and an NMOS region, forming a thermal oxide layer on the strained Si layer, selectively removing the thermal oxide layer and strained Si layer from the PMOS region, depositing a layer of high-k material on the layer of SiGe in the PMOS region and then forming gate electrodes in the PMOS and NMOS regions.

摘要翻译： 具有平衡驱动电流的CMOS器件由基于SiGe的PMOS晶体管和沉积的高k栅极电介质形成。 实施例包括在SiGe层上形成包括应变硅层的复合衬底，形成限定PMOS区域的隔离区域和在应变Si层上形成热氧化物层的NMOS区域，选择性地去除热氧化物层和应变Si 层，在PMOS区域中的SiGe层上沉积高k材料层，然后在PMOS和NMOS区域中形成栅电极。

公开(公告)号：US06955969B2

公开(公告)日：2005-10-18

申请号：US10654497

申请日：2003-09-03

申请人： Ihsan J. Djomehri ,  Jung-Suk Goo ,  Srinath Krishnan ,  Witold P. Maszara ,  James N. Pan ,  Qi Xiang

发明人： Ihsan J. Djomehri ,  Jung-Suk Goo ,  Srinath Krishnan ,  Witold P. Maszara ,  James N. Pan ,  Qi Xiang

IPC分类号： H01L21/20 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/336 ,  H01L21/338

CPC分类号： H01L29/0847 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/78

摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.

摘要翻译： 形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

公开(公告)号：US06902991B2

公开(公告)日：2005-06-07

申请号：US10282513

申请日：2002-10-24

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/337 ,  H01L29/10 ,  H01L21/04

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/66893

摘要： A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This construction effectively provides dual substrates at both sides of the strained silicon layer to support the tensile strain of the strained silicon layer and to resist the formation of misfit dislocations that may be induced by temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown on substrates having a given germanium content is effectively doubled. The silicon germanium layer overlying the strained silicon layer may be maintained during MOSFET processing to resist creation of misfit dislocations in the strained silicon layer up to the time of formation of gate insulating material.

摘要翻译： 在硅锗层上生长应变硅层，并且在单个连续原位沉积工艺中，在应变硅层上生长第二层硅锗。 硅锗的两层可以用应变硅原位生长。 这种结构在应变硅层的两侧有效地提供了两个基板，以支撑应变硅层的拉伸应变，并且抵抗可能在加工过程中温度变化引起的失配位错的形成。 因此，可以在具有给定锗含量的衬底上生长的应变硅的临界厚度被有效地加倍。 覆盖应变硅层的硅锗层可以在MOSFET加工过程中保持，以抵抗在形成栅极绝缘材料时产生应变硅层中的失配位错。

公开(公告)号：US06902977B1

公开(公告)日：2005-06-07

申请号：US10678445

申请日：2003-10-03

申请人： George J. Kluth ,  Joong S. Jeon ,  Qi Xiang ,  Huicai Zhong

发明人： George J. Kluth ,  Joong S. Jeon ,  Qi Xiang ,  Huicai Zhong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28035 ,  H01L21/28194 ,  H01L29/4925 ,  H01L29/517

摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a high-k dielectric layer over the substrate. The high-k dielectric layer may be, for example, hafnium oxide or zirconium oxide. The method further comprises forming a first polysilicon layer over the high-k dielectric layer, where the first polysilicon layer is formed by utilizing a precursor does not comprise hydrogen. The first polysilicon layer can have a thickness of between approximately 50.0 Angstroms and approximately 200.0 Angstroms, for example. According to this exemplary embodiment, the method can further comprise forming a second polysilicon layer over the first polysilicon layer. The second polysilicon layer may be formed, for example, by utilizing a precursor that comprises hydrogen, where the first polysilicon layer prevents the hydrogen from interacting with the high-k dielectric layer.

摘要翻译： 根据一个示例性实施例，在衬底上形成场效应晶体管的方法包括在衬底上形成高k电介质层的步骤。 高k电介质层可以是例如氧化铪或氧化锆。 该方法还包括在高k电介质层上形成第一多晶硅层，其中通过利用前体形成第一多晶硅层不包含氢。 例如，第一多晶硅层可以具有在约50.0埃和约200.0埃之间的厚度。 根据该示例性实施例，该方法还可以包括在第一多晶硅层上形成第二多晶硅层。 第二多晶硅层可以例如通过利用包含氢的前体形成，其中第一多晶硅层防止氢与高k电介质层相互作用。

公开(公告)号：US06900143B1

公开(公告)日：2005-05-31

申请号：US10658963

申请日：2003-09-09

申请人： James N. Pan ,  Jung-Suk Goo ,  Qi Xiang

发明人： James N. Pan ,  Jung-Suk Goo ,  Qi Xiang

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/461 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28525 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

摘要： The thermal conductivity of strained silicon MOSFETs and strained silicon SOI MOSFETs is improved by providing a silicon germanium carbide thermal dissipation layer beneath a silicon germanium layer on which strained silicon is grown. The silicon germanium carbide thermal dissipation layer has a higher thermal conductivity than silicon germanium, thus providing more efficient removal of thermal energy generated in active regions.

摘要翻译： 通过在其上生长应变硅的硅锗层之下提供硅碳化硅散热层来改善应变硅MOSFET和应变硅SOI MOSFET的导热性。 硅碳化硅散热层具有比硅锗更高的热导率，从而提供更有效地去除在活性区域中产生的热能。

公开(公告)号：US20050095807A1

公开(公告)日：2005-05-05

申请号：US10755746

申请日：2004-01-12

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： C12N5/0797 ,  H01L21/308 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/76

CPC分类号： H01L21/02238 ,  C12N5/0623 ,  C12N2501/11 ,  C12N2501/115 ,  C12N2501/91 ,  C12N2501/999 ,  H01L21/02255 ,  H01L21/3081 ,  H01L21/31658 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is formed in a selective epitaxial growth (SEG) process. The SEG process can be a CVD or MBE process. Capping layers can be used above the strained silicon layer.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由在选择性外延生长（SEG）工艺中形成的半导体或金属层形成。 SEG过程可以是CVD或MBE过程。 可以在应变硅层之上使用封盖层。

公开(公告)号：US20050054149A1

公开(公告)日：2005-03-10

申请号：US10654689

申请日：2003-09-04

申请人： Qi Xiang ,  Huicai Zhong ,  Jung-Suk Goo ,  Allison Holbrook ,  Joong Jeon ,  George Kluth

发明人： Qi Xiang ,  Huicai Zhong ,  Jung-Suk Goo ,  Allison Holbrook ,  Joong Jeon ,  George Kluth

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

摘要翻译： 根据一个示例性实施例，一种用于在衬底上将第一和第二金属层集成以形成双金属NMOS栅极和PMOS栅极的方法包括在衬底的NMOS区域和PMOS区域上沉积介电层。 该方法还包括在电介质层上沉积第一金属层。 该方法还包括在第一金属层上沉积第二金属层。 该方法还包括在衬底的NMOS区域中注入氮气，并将第一金属层的第一部分转变为金属氧化物层，并将第一金属层的第二部分转换为金属氮化物层。 该方法还包括形成NMOS栅极和PMOS栅极，其中NMOS栅极包括一段金属氮化物层，PMOS栅极包括金属氧化物层的一段。

公开(公告)号：US06812106B1

公开(公告)日：2004-11-02

申请号：US10341366

申请日：2003-01-14

申请人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

发明人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606

摘要： Dopant deactivation of source/drain extensions during silicidation is reduced by forming deep source/drain regions using a disposable dummy gate as a mask, forming metal silicide layers on the deep source/drain regions, removing the dummy gate and then forming the source/drain extensions using laser thermal annealing. Embodiments include angular ion implantation, after removing the dummy gate, to form spaced apart pre-amorphized regions, ion implanting to form source/drain extension implants extending deeper into the substrate than the pre-amorphized regions, and then laser thermal annealing to activate the source/drain extensions having a higher impurity concentration at the main surface of the substrate than deeper into the substrate. Subsequent processing includes forming sidewall spacers, a gate dielectric layer and then the gate electrode.

摘要翻译： 通过使用一次性虚拟栅极作为掩模形成深源极/漏极区域，在深度源极/漏极区域形成金属硅化物层，去除虚拟栅极，然后形成源极/漏极 扩展使用激光热退火。 实施例包括角度离子注入，在去除虚拟栅极之后，形成间隔开的非晶化区域，离子注入以形成比预非晶化区域更深地延伸到衬底中的源极/漏极延伸植入物，然后激光热退火以激活 源/漏扩展在衬底的主表面具有较高的杂质浓度，而不是深入衬底。 随后的处理包括形成侧壁间隔物，栅介质层，然后形成栅电极。