公开(公告)号：US20050124130A1

公开(公告)日：2005-06-09

申请号：US11036860

申请日：2005-01-13

申请人： Leo Mathew ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Ramachandran Muralidhar

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7842 ,  Y10S257/90

摘要： A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

摘要翻译： 半导体工艺和所得晶体管包括在栅电极（116）的任一侧上形成导电延伸间隔物（146,150）。 导电延伸部（146,150）和栅电极116被独立地掺杂，使得每个结构可以是n型或p型。 源极/漏极区域（156）被植入在间隔物（146,150）的任一侧上。 间隔物（146,150）可以通过使用第一成角度的植入物（132）来掺杂第一延伸间隔物（146）和第二成角度的植入物（140）以掺杂第二间隔物（150）来独立地掺杂。 在一个实施例中，使用不同掺杂的延伸间隔物（146,150）消除了对阈值调整通道植入物的需要。

公开(公告)号：US20050059213A1

公开(公告)日：2005-03-17

申请号：US10663621

申请日：2003-09-16

申请人： Robert Steimle ,  Ramachandran Muralidhar ,  Wayne Paulson ,  Rajesh Rao ,  Bruce White ,  Erwin Prinz

发明人： Robert Steimle ,  Ramachandran Muralidhar ,  Wayne Paulson ,  Rajesh Rao ,  Bruce White ,  Erwin Prinz

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/115 ,  H01L29/423

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332

摘要： A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.

公开(公告)号：US06831310B1

公开(公告)日：2004-12-14

申请号：US10705504

申请日：2003-11-10

申请人： Leo Mathew ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Ramachandran Muralidhar

IPC分类号： H01L2980

CPC分类号： H01L27/108 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/785 ,  H01L29/7881

摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

摘要翻译： 晶体管（10）形成有三个可分别控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 通道侧壁上的电介质可以不同于通道顶部的电介质。 选择性地制造到源极，漏极和三个栅极的电接触。 通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。 当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。 当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

公开(公告)号：US06784103B1

公开(公告)日：2004-08-31

申请号：US10442500

申请日：2003-05-21

申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar

发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar

IPC分类号： H01L2144

CPC分类号： B82Y10/00 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28273 ,  H01L29/42332

摘要： Nanocrystals (22) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (22) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.

摘要翻译： 纳米晶体（22）形成在半导体中，例如在具有浮动栅极的存储器中。 电介质（18）覆盖在衬底（12）上并且被放置在化学气相沉积室（34）中。 第一前体气体，例如乙硅烷（36）在第一阶段期间流入化学气相沉积室，以使化学气相沉积室内存在的第一预定处理条件第一次使介质上的纳米晶体（22）成核 期。 第二前体气体，例如硅烷，在第一阶段之后的第二阶段期间流入化学气相沉积室，以在第二时间段内在化学气相沉积室内存在的第二预定处理条件下生长纳米晶体。

公开(公告)号：US06413819B1

公开(公告)日：2002-07-02

申请号：US09595821

申请日：2000-06-16

申请人： Sufi Zafar ,  Ramachandran Muralidhar ,  Bich-Yen Nguyen ,  Sucharita Madhukar ,  Daniel T. Pham ,  Michael A. Sadd ,  Chitra K. Subramanian

发明人： Sufi Zafar ,  Ramachandran Muralidhar ,  Bich-Yen Nguyen ,  Sucharita Madhukar ,  Daniel T. Pham ,  Michael A. Sadd ,  Chitra K. Subramanian

IPC分类号： H01L21336

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/7883 ,  H01L29/7888

摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).

摘要翻译： 提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。 该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。 然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。 该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。 一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。 在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。 然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。 然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

公开(公告)号：US06330184B1

公开(公告)日：2001-12-11

申请号：US09659105

申请日：2000-09-11

申请人： Bruce E. White ,  Bo Jiang ,  Ramachandran Muralidhar

发明人： Bruce E. White ,  Bo Jiang ,  Ramachandran Muralidhar

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  H01L29/7887

摘要： A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots (108) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are possible because the read current for the memory cell is different when the dots are programmed near the source region or near the drain region. Embodiments may use two different potentials for power supplies or three different potentials. The two-potential embodiment simplifies the design, whereas the three-potential embodiment has a reduced risk of disturb problems in adjacent unselected memory cells (100B, 100C, and 100D).

摘要翻译： 一种操作包括具有不连续存储元件的第一存储单元或代替常规浮动栅极的点的半导体器件的方法可被编程为三种不同状态中的至少一种。 不同的状态是可能的，因为当点被编程在源极区域附近或靠近漏极区域时，存储器单元的读取电流是不同的。 实施例可以使用两种不同的电源或三种不同的电位。 双电位实施例简化了设计，而三电位实施例降低了相邻未选择的存储单元（100B，100C和100D）中的干扰问题的风险。

公开(公告)号：US08575588B2

公开(公告)日：2013-11-05

申请号：US13238791

申请日：2011-09-21

申请人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

IPC分类号： H01L45/00

CPC分类号： H01L45/1675 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

摘要翻译： 形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。 形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。 当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。 当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

公开(公告)号：US08525169B1

公开(公告)日：2013-09-03

申请号：US13572289

申请日：2012-08-10

申请人： Daniel C. Edelstein ,  Stephen M. Gates ,  Edward W. Kiewra ,  Satyanarayana V. Nitta ,  Ramachandran Muralidhar ,  Dirk Pfeiffer

发明人： Daniel C. Edelstein ,  Stephen M. Gates ,  Edward W. Kiewra ,  Satyanarayana V. Nitta ,  Ramachandran Muralidhar ,  Dirk Pfeiffer

IPC分类号： H01L21/66 ,  H01L21/74

CPC分类号： H01L23/544 ,  H01L21/268 ,  H01L21/76894 ,  H01L22/14 ,  H01L23/5226 ,  H01L23/53271 ,  H01L23/573 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2924/0002 ,  H04L9/3247 ,  H04L9/3278 ,  H01L2924/00

摘要： The present disclosure relates to a secure device having a physical unclonable function. The device includes an integrated circuit having a semiconducting material in at least one via in a backend of the integrated circuit. The present disclosure also relates to a method for manufacturing a secure device having a physical unclonable function. The method includes providing an integrated circuit and adding a semiconducting material to at least one via in a backend of the integrated circuit. In some instances a property of the semiconducting material in the at least one via is measured to derive a signature.

摘要翻译： 本公开涉及具有物理不可克隆功能的安全装置。 该器件包括在集成电路的后端中的至少一个通孔中具有半导体材料的集成电路。 本公开还涉及一种用于制造具有物理不可克隆功能的安全装置的方法。 该方法包括提供集成电路并将集成电路的后端中的至少一个通孔添加半导体材料。 在一些情况下，测量至少一个通孔中的半导体材料的特性以导出签名。

公开(公告)号：US08373221B2

公开(公告)日：2013-02-12

申请号：US11964309

申请日：2007-12-26

申请人： Robert F. Steimle ,  Ramachandran Muralidhar ,  Bruce E. White

发明人： Robert F. Steimle ,  Ramachandran Muralidhar ,  Bruce E. White

IPC分类号： H01L29/792

CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11573

摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.

摘要翻译： 集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。 集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。 集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。 当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。 在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。

公开(公告)号：US20130032883A1

公开(公告)日：2013-02-07

申请号：US13198255

申请日：2011-08-04

申请人： Kevin K. Chan ,  Young-Hee Kim ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Dae-Gyu Park ,  Xinhui Wang ,  Min Yang

发明人： Kevin K. Chan ,  Young-Hee Kim ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Dae-Gyu Park ,  Xinhui Wang ,  Min Yang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/24

CPC分类号： H01L21/31 ,  H01L21/0228 ,  H01L21/2254 ,  H01L29/165 ,  H01L29/365 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66803 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785

摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.