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    Programming mode selection with JTAG circuits
    93.
    发明授权
    Programming mode selection with JTAG circuits 失效
    使用JTAG电路进行编程模式选择

    公开(公告)号：US06421812B1

    公开(公告)日：2002-07-16

    申请号：US09094186

    申请日：1998-06-09

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    IPC分类号： G06F1750

    CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

    摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

    摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

    High performance memory interface circuit architecture
    95.
    发明授权
    High performance memory interface circuit architecture 有权
    高性能存储器接口电路架构

    公开(公告)号：US08593195B1

    公开(公告)日：2013-11-26

    申请号：US13614526

    申请日：2012-09-13

    申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    IPC分类号： H03H11/16

    CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

    摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

    摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

    MEMORY CONTROLLERS WITH DYNAMIC PORT PRIORITY ASSIGNMENT CAPABILITIES
    96.
    发明申请
    MEMORY CONTROLLERS WITH DYNAMIC PORT PRIORITY ASSIGNMENT CAPABILITIES 有权
    具有动态端口优先级分配能力的内存控制器

    公开(公告)号：US20120311277A1

    公开(公告)日：2012-12-06

    申请号：US13151101

    申请日：2011-06-01

    申请人： Michael H.M. Chu ,  Jeffrey Schulz ,  Chiakang Sung ,  Ravish Kapasi

    发明人： Michael H.M. Chu ,  Jeffrey Schulz ,  Chiakang Sung ,  Ravish Kapasi

    IPC分类号： G06F12/08

    CPC分类号： G06F13/1626 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/18

    摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.

    摘要翻译： 可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控​​制器。 存储器控制器可以通过具有相关优先级值的端口从主设备接收存储器访问请求，并通过配置系统存储器来响应存储器访问请求来满足存储器访问请求。 为了在存储器控制器接收并满足存储器访问请求的同时动态地修改相关联的优先级值，可以提供动态地更新存储器控制器端口的优先级值的优先级值更新模块。 优先级值更新模块可以根据更新信号和系统时钟向更新的优先级值提供更新的更新寄存器。 优先级值可以由移位寄存器，存储器映射寄存器提供，或由主器件与每个存储器访问请求一起提供。

    Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop
    97.
    发明授权
    Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop 有权
    用于产生PVT补偿相位偏移以提高锁定环路精度的技术

    公开(公告)号：US08237475B1

    公开(公告)日：2012-08-07

    申请号：US12248031

    申请日：2008-10-08

    申请人： Pradeep Nagarajan ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

    发明人： Pradeep Nagarajan ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0805 ,  H03L7/0814 ,  H03L7/0816

    摘要： A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.

    摘要翻译： 电路包括锁定环和相位偏移电路。 锁定环产生用于控制锁定环路中的第一延迟的第一控制信号。 相位偏移电路延迟由第二控制信号控制的第二延迟的输入信号以产生延迟的信号。 相位偏移电路通过调整第一控制信号来产生第二控制信号，以提高相对于目标相位的延迟信号的精度。 第二控制信号补偿由电路的过程，电源电压和温度中的至少一个的变化引起的第二延迟的变化的至少一部分。

    Techniques for providing reduced duty cycle distortion
    98.
    发明授权
    Techniques for providing reduced duty cycle distortion 有权
    提供减少占空比失真的技术

    公开(公告)号：US08130016B2

    公开(公告)日：2012-03-06

    申请号：US12642502

    申请日：2009-12-18

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/134 ,  H03K5/1565 ,  H03K2005/00065

    摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.

    摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。 每个可变延迟块和固定延迟块都是反相的。

    DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS
    99.
    发明申请
    DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS 有权
    用于集成电路中的存储器接口的占空比校正电路

    公开(公告)号：US20110175657A1

    公开(公告)日：2011-07-21

    申请号：US12690064

    申请日：2010-01-19

    申请人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

    发明人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

    摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

    摘要翻译： 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。 时钟信号分为两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路耦合到每个时钟信号。 每个延迟电路产生相应时钟信号的延迟版本。 耦合校正器电路以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

    Method and apparatus for quantifying and minimizing skew between signals
    100.
    发明授权
    Method and apparatus for quantifying and minimizing skew between signals 失效
    用于量化和最小化信号之间的偏差的方法和装置

    公开(公告)号：US07671579B1

    公开(公告)日：2010-03-02

    申请号：US11470898

    申请日：2006-09-07

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    IPC分类号： G01R23/175 ,  G08B23/00

    CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

    摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

    摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。