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1647 条记录 (耗时 0.037 秒)

    Integrated circuit inductor with a magnetic core
    91.
    发明授权
    Integrated circuit inductor with a magnetic core 有权

    公开(公告)号：US06756875B2

    公开(公告)日：2004-06-29

    申请号：US10357528

    申请日：2003-02-03

    申请人： Kie Y. Ahn ,  Leonard Forbes

    发明人： Kie Y. Ahn ,  Leonard Forbes

    IPC分类号： H01F500

    CPC分类号： H01F41/046 ,  H01F5/003 ,  H01F17/0033 ,  H01F17/045 ,  H01L28/10 ,  Y10T29/4902

    摘要： An inductor is fabricated on a substrate having a top surface and a bottom surface. The inductor includes a plurality of holes extending through the substrate, wherein the plurality of holes interconnect the top surface and the bottom surface of the substrate. The inductor also includes a plurality of conductive posts formed in the plurality of holes and a plurality of conductive segments formed on the top surface and on the bottom surface that interconnect the conductive posts such that a continuous conductive coil is formed. The inductor also includes a magnetic core that occupies substantially the entire volume enclosed by the conductive coil.

    Transistor with variable electron affinity gate and methods of fabrication and use
    92.
    发明授权
    Transistor with variable electron affinity gate and methods of fabrication and use 失效

    公开(公告)号：US06746893B1

    公开(公告)日：2004-06-08

    申请号：US09256643

    申请日：1999-02-23

    申请人： Leonard Forbes ,  Kie Y. Ahn

    发明人： Leonard Forbes ,  Kie Y. Ahn

    IPC分类号： H01L2100

    CPC分类号： H01L29/4983 ,  H01L21/2807 ,  H01L21/28273 ,  H01L29/42324 ,  H01L31/113 ,  Y10S438/931

    摘要： A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.

    Static pass transistor logic with transistors with multiple vertical gates
    93.
    发明授权
    Static pass transistor logic with transistors with multiple vertical gates 有权
    具有多个垂直栅极的晶体管的静态晶体管逻辑

    公开(公告)号：US06744082B1

    公开(公告)日：2004-06-01

    申请号：US09580901

    申请日：2000-05-30

    申请人： Leonard Forbes ,  Kie Y. Ahn

    发明人： Leonard Forbes ,  Kie Y. Ahn

    IPC分类号： H01L29792

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/1052 ,  H01L29/42332 ,  H01L29/7831 ,  H01L29/7887

    摘要： Systems and methods are provided for static pass transistor logic having transistors with multiple vertical gates. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input. The novel static pass transistor of the present invention includes a transistor which has a horizontal depletion mode channel region between a single source and drain region. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. According to the present invention, there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates.

    摘要翻译： 为具有多个垂直栅极的晶体管的静态晶体管逻辑提供了系统和方法。 多个垂直栅极被限定为使得多个逻辑输入仅需要单个晶体管。 因此，每个逻辑输入都需要最小的表面积。 本发明的新型静态通过晶体管包括在单个源极和漏极区域之间具有水平耗尽模式沟道区的晶体管。 多个垂直栅极位于耗尽模式沟道区的不同部分上方。 至少一个垂直栅极位于耗尽模式沟道区的第一部分之上，并且通过第一厚度绝缘体材料与沟道区分离。 垂直门中的至少一个位于沟道区的第二部分上方并且通过第二厚度的绝缘体材料与沟道区分离。 根据本发明，没有与每个输入相关联的源极和漏极区域，并且由于边缘限定的垂直栅极，栅极具有亚光刻水平尺寸。

    Current mode signal interconnects and CMOS amplifier
    94.
    发明授权
    Current mode signal interconnects and CMOS amplifier 有权
    电流模式信号互连和CMOS放大器

    公开(公告)号：US06737887B2

    公开(公告)日：2004-05-18

    申请号：US09898688

    申请日：2001-07-03

    申请人： Leonard Forbes ,  Kie Y. Ahn

    发明人： Leonard Forbes ,  Kie Y. Ahn

    IPC分类号： H03K190175

    CPC分类号： H04L25/0298 ,  H04L25/0282 ,  H04L25/0294

    摘要： This invention provides a structure and method for improved transmission line operation on integrated circuits. A first embodiment of this invention provides a current mode signaling technique over transmission lines formed having a lower characteristic impedance than conventional CMOS transmission lines. The low impedance transmission lines of the present invention are more amenable to signal current interconnections over longer interconnection lines. An interconnection on an integrated circuit is described in which a first end of a transmission line is coupled to a driver. The transmission line is terminated at a second end with a low input impedance CMOS technology. In one embodiment, the low input impedance CMOS technology is a current sense amplifier which is input impedance matched to the transmission line. This minimizes reflections and ringing, cross talk and noise as well as allows for a very fast interconnection signal response. A second embodiment of the present invention includes a novel current sense amplifier in which feedback is introduced to lower the input impedance of the current sense amplifier. In this embodiment, the novel current sense amplifier is employed together with the current signaling technique of the present invention. The novel low input impedance CMOS circuit described here provides an improved and efficiently fabricated technique for terminating low impedance transmission lines on CMOS integrated circuits.

    摘要翻译： 本发明提供了一种用于改进集成电路上的传输线操作的结构和方法。 本发明的第一实施例提供了一种在传统线路上形成的电流模式信令技术，该传输线路具有比常规CMOS传输线路更低的特性阻抗。 本发明的低阻抗传输线更适合于在更长的互连线上信号电流互连。 描述集成电路中的互连，其中传输线的第一端耦合到驱动器。 传输线在第二端以低输入阻抗CMOS技术终止。 在一个实施例中，低输入阻抗CMOS技术是与传输线匹配的输入阻抗的电流检测放大器。 这使反射和振铃，串扰和噪声最小化，并且允许非常快的互连信号响应。本发明的第二实施例包括一种新颖的电流读出放大器，其中引入反馈以降低电流感测放大器的输入阻抗 。 在本实施例中，新颖的电流检测放大器与本发明的当前信令技术一起使用。 这里描述的新型低输入阻抗CMOS电路提供了用于在CMOS集成电路上终止低阻抗传输线的改进且有效的制造技术。

    Carburized silicon gate insulators for integrated circuits
    96.
    发明授权
    Carburized silicon gate insulators for integrated circuits 失效

    公开(公告)号：US06731531B1

    公开(公告)日：2004-05-04

    申请号：US09650553

    申请日：2000-08-30

    申请人： Leonard Forbes ,  Kie Y. Ahn

    发明人： Leonard Forbes ,  Kie Y. Ahn

    IPC分类号： G11C1124

    CPC分类号： G11C16/0466 ,  H01L21/28194 ,  H01L21/28273 ,  H01L27/10852 ,  H01L28/40 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/51 ,  Y10S438/931

    摘要： Silicon carbide films are grown by carburization of silicon to form insulative films. In one embodiment, the film is used to provide a gate insulator for a field effect transistor. The film is grown in a microwave-plasma-enhanced chemical vapor deposition (MPECVD) system. A silicon substrate is first etched in dilute HF solution and rinsed. The substrate is then placed in a reactor chamber of the MPECVD system in hydrogen along with a carbon containing gas. The substrate is then inserted into a microwave generated plasma for a desired time to grow the film. The microwave power varies depending on substrate size. The growth of the film may be continued following formation of an initial film via the above process by using a standard CVD deposition of amorphous SiC. The film may be used to form gate insulators for FET transistors in DRAM devices and flash type memories. It may be formed as dielectric layers in capacitors in the same manner.

    Method of forming an optical fiber interconnect through a semiconductor wafer
    97.
    发明授权
    Method of forming an optical fiber interconnect through a semiconductor wafer 失效
    通过半导体晶片形成光纤互连的方法

    公开(公告)号：US06723577B1

    公开(公告)日：2004-04-20

    申请号：US09650569

    申请日：2000-08-30

    申请人： Joseph E. Geusic ,  Kie Y. Ahn ,  Leonard Forbes

    发明人： Joseph E. Geusic ,  Kie Y. Ahn ,  Leonard Forbes

    IPC分类号： H01L2100

    CPC分类号： G02B6/43 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

    摘要翻译： 具有形成在高纵横比孔中的多根光纤的集成电路。 高纵横比孔延伸穿过半导体晶片。 光纤包括形成在高纵横比孔中的包覆层和芯。 这些光纤用于在半导体晶片上的功能电路和晶片背面或晶片之下的功能电路之间传输信号。

    Integrated circuit inductors
    98.
    发明授权
    Integrated circuit inductors 有权

    公开(公告)号：US06701607B2

    公开(公告)日：2004-03-09

    申请号：US10102070

    申请日：2002-03-19

    申请人： Kie Y. Ahn ,  Leonard Forbes

    发明人： Kie Y. Ahn ,  Leonard Forbes

    IPC分类号： H01F706

    CPC分类号： H01F17/0033 ,  H01F27/2804 ,  H01F37/00 ,  H01L27/08 ,  Y10S257/924 ,  Y10T29/4902 ,  Y10T29/49037 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075

    摘要： The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic metals, alloys, and oxides. The inductor is compatible with integrated circuit manufacturing techniques and eliminates the need in many systems and circuits for large off chip inductors. A sense and measurement coil, which is fabricated on the same substrate as the inductor, provides the capability to measure the magnetic field or flux produced by the inductor. This on chip measurement capability supplies information that permits circuit engineers to design and fabricate on chip inductors to very tight tolerances.

    Buried ground plane for high performance system modules
    99.
    发明授权
    Buried ground plane for high performance system modules 失效
    埋地面为高性能系统模块

    公开(公告)号：US06670703B1

    公开(公告)日：2003-12-30

    申请号：US09515083

    申请日：2000-02-28

    申请人： Kie Y. Ahn ,  Leonard Forbes

    发明人： Kie Y. Ahn ,  Leonard Forbes

    IPC分类号： H01L2352

    CPC分类号： H01L23/66 ,  H01L21/4803 ,  H01L21/4846 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/96 ,  H01L2924/00

    摘要： A method and apparatus for producing buried ground planes in a silicon substrate for use in system modules is disclosed. Conductor patterns arc printed on the surface of the silicon substrate. Pores are created in the printed conductor patterns by a chemical anodization process. The pores are then filled with a conductive metal, such as tungsten, molybdenum, or copper by a selective deposition process to produce a low impedance ground buried in the substrate.

    摘要翻译： 公开了一种用于在用于系统模块的硅衬底中产生埋地面的方法和装置。 导体图案电弧印刷在硅衬底的表面上。 通过化学阳极氧化处理在印刷的导体图案中产生孔。 然后通过选择性沉积工艺用导电金属（例如钨，钼或铜）填充孔，以产生埋在衬底中的低阻抗地层。

    Low loss high Q inductor
    100.
    发明授权
    Low loss high Q inductor 有权

    公开(公告)号：US06656813B2

    公开(公告)日：2003-12-02

    申请号：US09982959

    申请日：2001-10-22

    申请人： Kie Y. Ahn ,  Leonard Forbes

    发明人： Kie Y. Ahn ,  Leonard Forbes

    IPC分类号： H01L21607

    CPC分类号： H01L27/08 ,  H01F17/0006 ,  H01F27/34 ,  H01F41/041 ,  H01L28/10

    摘要： A high Q inductive element with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching in bulk silicon. The support elements, which may have different configurations, such as walls or columns, provide mechanical stability to the inductive loops and reduce the parasitic capacitance and the losses to the substrate.