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102 条记录 (耗时 0.027 秒)

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    91.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06333660B2

    公开(公告)日：2001-12-25

    申请号：US09780475

    申请日：2001-02-12

    申请人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    IPC分类号： H03K3013

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor integrated circuit and method of controlling same
    92.
    发明授权
    Semiconductor integrated circuit and method of controlling same 有权
    半导体集成电路及其控制方法

    公开(公告)号：US06324113B1

    公开(公告)日：2001-11-27

    申请号：US09577498

    申请日：2000-05-24

    申请人： Hiroyoshi Tomita

    发明人： Hiroyoshi Tomita

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： A semiconductor integrated circuit comprising: a pair of memory cores in which identical data are written; a refresh signal generating circuit; a refresh controlling circuit; and a read controlling circuit. The memory cores are operated during each predetermined period as refresh cores for performing a refresh operation and as read cores for performing a read operation. The refresh core performs refresh and write operations. The read core performs read and write operations. The write cycle time defined as an operation specification is set longer than the time necessary for each of the memory cores to perform a write operation. Therefore, during the refresh core, the time difference between the write cycle and the write operation is summed up during a plurality of write cycles to create a predetermined time margin. This time margin is utilized to perform a refresh operation so that the performance of the refresh operation, in conflict with the write operation, does not show to the exterior of the semiconductor integrated circuit. That is, even if a write operation is performed throughout the refresh core period, it is possible to prevent the data in the memory cores from being damaged. This enables users to use the semiconductor integrated circuit without taking refresh operations into consideration.

    摘要翻译： 一种半导体集成电路，包括：一对存储器核，其中写入相同的数据; 刷新信号发生电路; 刷新控制电路; 和读控制电路。 在每个预定时段期间，存储器核心作为用于执行刷新操作的刷新核心以及用于执行读取操作的读取核心。 刷新内核执行刷新和写入操作。 读核心执行读写操作。 定义为操作规范的写周期时间被设置为比每个存储器核执行写操作所需的时间长。 因此，在刷新核心期间，在多个写周期期间将写入周期和写入操作之间的时间差相加以创建预定的时间裕度。 该时间裕度用于执行刷新操作，使得与写入操作冲突的刷新操作的性能不显示到半导体集成电路的外部。 也就是说，即使在刷新核心周期执行写入操作，也可以防止存储器核心中的数据被损坏。 这使得用户能够使用半导体集成电路而不考虑刷新操作。

    Semiconductor device reconciling different timing signals
    94.
    发明授权
    Semiconductor device reconciling different timing signals 有权
    半导体器件协调不同的定时信号

    公开(公告)号：US06292428B1

    公开(公告)日：2001-09-18

    申请号：US09240007

    申请日：1999-01-29

    申请人： Hiroyoshi Tomita ,  Tatsuya Kanda

    发明人： Hiroyoshi Tomita ,  Tatsuya Kanda

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18

    摘要： A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

    摘要翻译： 与时钟信号同步地接收地址并与选通信号同步地接收数据的半导体器件包括地址锁存电路，响应于时钟信号依次选择地址锁存电路之一的第一控制电路，以及 控制所选择的一个地址锁存电路以响应于时钟信号锁存对应的一个地址;以及第二控制电路，其响应于选通信号依次选择一个地址锁存电路，并且控制 所选择的一个地址锁存电路响应于选通信号输出对应的一个地址。

    Clock signal generator for an integrated circuit
    95.
    发明授权
    Clock signal generator for an integrated circuit 有权
    用于集成电路的时钟信号发生器

    公开(公告)号：US06275086B1

    公开(公告)日：2001-08-14

    申请号：US09385007

    申请日：1999-08-27

    申请人： Hiroko Douchi ,  Hiroyoshi Tomita

    发明人： Hiroko Douchi ,  Hiroyoshi Tomita

    IPC分类号： H03K513

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  H03K5/2481

    摘要： A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers. A logic gate receives the first enable signal and the first internal clock signal and controls the output of the first internal clock signal.

    摘要翻译： 对双倍数据速率SDRAM（DDR-SDRAM）特别有用的时钟信号发生器包括两个或更多个时钟信号输入缓冲器和使能信号输入缓冲器。 时钟信号发生器产生以基本上不同的定时波动的内部时钟信号，但是内部时钟信号相对于验证和无效定时的关系是恒定的。 锁存电路根据来自第一个时钟信号缓冲器的第一内部时钟信号来锁存来自使能信号缓冲器的使能信号。 连接到锁存电路的第一使能信号根据第一内部时钟信号保持锁存使能信号。 第二使能电路接收第一使能信号和第一内部时钟信号，并产生用于激活时钟信号缓冲器的第二使能信号。 逻辑门接收第一使能信号和第一内部时钟信号并控制第一内部时钟信号的输出。

    Integrated circuit device
    96.
    发明授权
    Integrated circuit device 有权
    集成电路器件

    公开(公告)号：US06266294B1

    公开(公告)日：2001-07-24

    申请号：US09304516

    申请日：1999-05-04

    申请人： Masahiro Yada ,  Hiroyoshi Tomita

    发明人： Masahiro Yada ,  Hiroyoshi Tomita

    IPC分类号： G11C800

    CPC分类号： G11C7/222 ,  G11C7/22

    摘要： According to the present invention, in an integrated circuit device for receiving an external clock signal and a clock enable signal and for supplying to an internal circuit an internal clock signal which has a predetermined phase relationship with the external clock signal, a DLL circuit for generating a delay clock signal, synchronized and in phase with the external clock signal, is operated continuously even in a low power consumption mode, and the provision of the delay clock signal to the internal circuit is halted. When the mode is switched from the low power consumption mode to the normal mode, the delay clock signal generated by the DLL circuit, which is operated continuously, is supplied as an internal clock signal to the internal circuit again.

    摘要翻译： 根据本发明，在用于接收外部时钟信号和时钟使能信号并用于向内部电路提供与外部时钟信号具有预定相位关系的内部时钟信号的集成电路装置中，用于产生 与外部时钟信号同步且同相的延迟时钟信号即使在低功耗模式下也连续工作，并且停止向内部电路提供延迟时钟信号。 当模式从低功耗模式切换到正常模式时，由连续操作的DLL电路产生的延迟时钟信号作为内部时钟信号被再次提供给内部电路。

    Semiconductor integrated circuit device
    97.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06225843B1

    公开(公告)日：2001-05-01

    申请号：US09385005

    申请日：1999-08-27

    申请人： Nobutaka Taniguchi ,  Hiroyoshi Tomita

    发明人： Nobutaka Taniguchi ,  Hiroyoshi Tomita

    IPC分类号： H03L700

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/089

    摘要： A semiconductor integrated circuit device includes a first delay circuit delaying a first clock signal, a second delay circuit delaying a second clock signal which has an inverted phase with respect to the first clock signal, a phase comparator outputting a phase error signal based on a comparison of the first clock signal and a feedback signal corresponding to an output signal from the first delay circuit, a delay control circuit generating a delay control signal based on the phase error signal, for variably controlling a delay quantity of the first and second delay circuits, and a timing adjusting circuit variably controlling a delay quantity of the second delay circuit by supplying the delay control signal to the second delay circuit at a timing synchronized to the second clock signal.

    摘要翻译： 半导体集成电路器件包括延迟第一时钟信号的第一延迟电路，延迟相对于第一时钟信号具有反相的第二时钟信号的第二延迟电路;基于比较器输出相位误差信号的相位比较器 所述第一时钟信号和对应于来自所述第一延迟电路的输出信号的反馈信号，延迟控制电路，基于所述相位误差信号产生延迟控制信号，用于可变地控制所述第一和第二延迟电路的延迟量， 以及定时调整电路，通过在与第二时钟信号同步的定时向第二延迟电路提供延迟控制信号，可变地控制第二延迟电路的延迟量。