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102 条记录 (耗时 0.038 秒)

    Integrated circuit device
    5.
    发明授权
    Integrated circuit device 有权
    集成电路器件

    公开(公告)号：US06194932B1

    公开(公告)日：2001-02-27

    申请号：US09383015

    申请日：1999-08-25

    申请人： Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Nobutaka Taniguchi

    发明人： Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Nobutaka Taniguchi

    IPC分类号： H03L700

    CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03L7/0814

    摘要： The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.

    摘要翻译： 本发明省略了DLL电路内部的可变延迟电路（图1中的10），而是产生产生第二参考时钟的定时同步电路。 定时同步电路将由分频器产生的第一参考时钟的相位移位到从另一个可变延迟电路产生的定时信号的定时，使得第二参考时钟与定​​时信号相匹配。 然后，相位比较器将分频的第一参考时钟与延迟第二参考时钟的可变时钟进行比较，并且控制可变延迟电路的延迟时间，使得两个时钟同相。 结果，可以省略一个可变延迟电路，并且可以配置使用分频时钟的DLL电路。

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    7.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06333660B2

    公开(公告)日：2001-12-25

    申请号：US09780475

    申请日：2001-02-12

    申请人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    IPC分类号： H03K3013

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor memory device and method of forming the same
    8.
    发明授权
    Semiconductor memory device and method of forming the same 失效
    半导体存储器件及其形成方法

    公开(公告)号：US5537354A

    公开(公告)日：1996-07-16

    申请号：US357307

    申请日：1994-12-14

    申请人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

    发明人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

    IPC分类号： G11C11/401 ,  F02B75/02 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C7/1072 ,  F02B2075/025

    摘要： A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.

    摘要翻译： 将SDRAM（同步动态随机存取存储器）制成低速型或高速型的方法包括以下步骤：确定SDRAM的预定电极的电连接，并为预定电极提供电压 由电气连接限定的电平，电压电平确定SDRAM是低速型还是高速型，其中低速类型可以以低时钟速率对具有 相同的行地址，并且高速类型可以以具有相同行地址和连续列地址的两个地址以高时钟速率执行同时写入操作。

    Semiconductor memory device for operating in synchronization with edge of clock signal
    9.
    发明授权
    Semiconductor memory device for operating in synchronization with edge of clock signal 有权
    用于与时钟信号的边沿同步操作的半导体存储器件

    公开(公告)号：US06510095B1

    公开(公告)日：2003-01-21

    申请号：US10073231

    申请日：2002-02-13

    申请人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

    发明人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2227

    摘要： A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response to reception timing of the command signal. Since the command signal can be received in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when a reception rate is the same as that of the conventional art. As a result of this, in a system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce power consumption of a clock synchronization circuit in the system, without reducing a data input/output rate for the semiconductor memory device.

    摘要翻译： 命令接收器电路与时钟信号的上升沿或下降沿同步地接收命令信号。 数据输入/输出电路与响应命令信号的接收定时而设置的时钟信号的边沿同步地开始读取数据的输出和写入数据的输入。 由于可以与时钟信号的两个边沿同步地接收命令信号，所以当接收速率与传统技术的接收速率相同时，可以将时钟周期减半。 结果，在安装了半导体存储器件的系统中，可以将系统时钟的频率减半，并且可以降低系统中时钟同步电路的功耗，而不减少数据输入/输出 速率为半导体存储器件。