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    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    2.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06333660B2

    公开(公告)日：2001-12-25

    申请号：US09780475

    申请日：2001-02-12

    申请人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    IPC分类号： H03K3013

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor memory device for operating in synchronization with edge of clock signal
    6.
    发明授权
    Semiconductor memory device for operating in synchronization with edge of clock signal 有权
    用于与时钟信号的边沿同步操作的半导体存储器件

    公开(公告)号：US06510095B1

    公开(公告)日：2003-01-21

    申请号：US10073231

    申请日：2002-02-13

    申请人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

    发明人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2227

    摘要： A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response to reception timing of the command signal. Since the command signal can be received in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when a reception rate is the same as that of the conventional art. As a result of this, in a system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce power consumption of a clock synchronization circuit in the system, without reducing a data input/output rate for the semiconductor memory device.

    摘要翻译： 命令接收器电路与时钟信号的上升沿或下降沿同步地接收命令信号。 数据输入/输出电路与响应命令信号的接收定时而设置的时钟信号的边沿同步地开始读取数据的输出和写入数据的输入。 由于可以与时钟信号的两个边沿同步地接收命令信号，所以当接收速率与传统技术的接收速率相同时，可以将时钟周期减半。 结果，在安装了半导体存储器件的系统中，可以将系统时钟的频率减半，并且可以降低系统中时钟同步电路的功耗，而不减少数据输入/输出 速率为半导体存储器件。

    LSI device with memory and logics mounted thereon
    8.
    发明授权
    LSI device with memory and logics mounted thereon 有权

    公开(公告)号：US06272069B1

    公开(公告)日：2001-08-07

    申请号：US09764446

    申请日：2001-01-19

    申请人： Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Masao Taguchi

    发明人： Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Masao Taguchi

    IPC分类号： G11C800

    摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.

    Self-test circuit and memory device incorporating it
    10.
    发明授权
    Self-test circuit and memory device incorporating it 有权
    自检电路和结合其的存储器件

    公开(公告)号：US06907555B1

    公开(公告)日：2005-06-14

    申请号：US09691115

    申请日：2000-10-19

    申请人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

    发明人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F12/16 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/12 ,  G11C29/44

    CPC分类号： G11C29/44

    摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

    摘要翻译： 本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。 当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。 此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息 关于这个比较的结果。 然后将该比较结果信息输出到外部。