公开(公告)号：US20200066318A1

公开(公告)日：2020-02-27

申请号：US16666045

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C8/12 ,  G06F12/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4096

Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

公开(公告)号：US20200028720A1

公开(公告)日：2020-01-23

申请号：US16536179

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

IPC: H04L25/49 ,  G11C7/10

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

公开(公告)号：US10446200B2

公开(公告)日：2019-10-15

申请号：US16058566

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G11C7/10 ,  H01L25/065 ,  H01L23/48 ,  G06F13/16 ,  G11C7/22 ,  G11C11/408 ,  G11C11/22

Abstract: Methods, systems, and apparatuses for a memory device that is configurable based on the type of substrate used to couple the memory device with a host device are described. The reconfigurable memory device may include a plurality of components for different configurations. Various components of the reconfigurable memory die may be activated/deactivated based on a type of substrate used in the memory device. The memory device may include an input/output (I/O) interface that is variously configurable. A first configuration may cause the memory device to communicate signals modulated using a first modulation scheme across a channel of a first width. A second configuration may cause the memory device to communicate signals modulated using a second modulation scheme across a channel of a second width. The I/O interface may include one or more switching components to selectively couple pins of a channel together and/or selectively couple components to various pins.

公开(公告)号：US20190215199A1

公开(公告)日：2019-07-11

申请号：US16353611

申请日：2019-03-14

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Feng Lin

IPC: H04L25/49 ,  G06F13/16 ,  G06F13/40 ,  H04L27/04 ,  G06F1/324 ,  H04L27/06

CPC classification number: H04L25/4917 ,  G06F1/324 ,  G06F13/1689 ,  G06F13/4068 ,  H04L27/04 ,  H04L27/06

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

公开(公告)号：US10277441B2

公开(公告)日：2019-04-30

申请号：US15893089

申请日：2018-02-09

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H04L25/03 ,  H04L27/08 ,  G11C7/10 ,  H04L27/04 ,  H04B1/04 ,  H03K19/00

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

公开(公告)号：US20190103148A1

公开(公告)日：2019-04-04

申请号：US15977813

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C8/12 ,  G06F12/02

CPC classification number: H04L27/04 ,  G06F12/0284 ,  G06F13/16 ,  G06F13/38 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/12 ,  G11C2207/101 ,  H04L25/49 ,  H04L27/02 ,  H04L27/06

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

公开(公告)号：US20190103143A1

公开(公告)日：2019-04-04

申请号：US15977815

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C7/10 ,  G06F1/32 ,  G06F13/42

CPC classification number: G11C7/1048 ,  G06F1/3234 ,  G06F13/42 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/4093

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US10229890B1

公开(公告)日：2019-03-12

申请号：US15872456

申请日：2018-01-16

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H01L23/64 ,  H04L27/04 ,  H04B5/00 ,  H01L23/00 ,  H01L25/065 ,  G11C11/16 ,  G11C11/401 ,  G11C11/22 ,  G11C13/00

Abstract: Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).

公开(公告)号：US10164817B2

公开(公告)日：2018-12-25

申请号：US15465421

申请日：2017-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean Gans ,  Randon Richards ,  Bruce W. Schober

IPC: H04L12/24 ,  H04L12/863 ,  H04L25/03

Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

公开(公告)号：US09922686B2

公开(公告)日：2018-03-20

申请号：US15159728

申请日：2016-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Huy T. Vo ,  Dirgha Khatri

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/10 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/22

Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.