公开(公告)号：US5372969A

公开(公告)日：1994-12-13

申请号：US845125

申请日：1992-03-03

申请人： Mehrdad M. Moslehi

发明人： Mehrdad M. Moslehi

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002

摘要： A high-performance "low-RC" multi-level interconnect technology has been conceived for advanced sub-0.5 .mu.m semiconductor technologies. The proposed structure and fabrication process has a number of significant characteristics: (i) compatible with various metal systems (Al, Cu, W, etc.), (ii) free-space interlevel dielectrics; (iii) compatible with standard semiconductor fabrication processes, (iv) excellent mechanical stability; and (v) compatible with hermetically sealed chip packaging techniques. Compared with an Al-based conventional interconnect technology, the new interconnect system can reduce the "RC" delay by a factor of .sup.- 6. The proposed interconnect technology offers major chip performance improvements such as lower power dissipation and higher operating frequencies. This technology is based on a manufacturable process to fabricate multilevel interconnect with free-space dielectrics and a technology scaling enabler.

摘要翻译： 高性能的“低RC”多层互连技术已被设计用于先进的次级0.5微米半导体技术。 所提出的结构和制造工艺具有许多显着特点：（i）与各种金属系统（Al，Cu，W等）兼容，（ii）自由空间层间电介质; （iii）兼容标准半导体制造工艺，（iv）优异的机械稳定性; 和（v）兼容密封芯片封装技术。 与基于Al的常规互连技术相比，新的互连系统可以将“RC”延迟降低到-6倍。 所提出的互连技术提供了主要的芯片性能改进，例如较低的功耗和较高的工作频率。 该技术基于可制造的工艺，用于制造具有自由空间电介质的多电平互连和技术缩放使能器。

公开(公告)号：US5367606A

公开(公告)日：1994-11-22

申请号：US56599

申请日：1993-08-10

申请人： Mehrdad M. Moslehi ,  Robert Matthews ,  Cecil J. Davis

发明人： Mehrdad M. Moslehi ,  Robert Matthews ,  Cecil J. Davis

IPC分类号： H01L21/26 ,  G01J5/00 ,  H01L21/00 ,  H01L21/324 ,  H05B3/62

CPC分类号： H01L21/67115

摘要： A multi-zone illuminator for processing semiconductor wafers is described which comprises a plurality of source lamps and dummy lamps embedded in the reflector side of a lamp housing. The source lamps are arranged in a plurality of concentric circular zones. The illuminator also comprises plurality of light pipes for receiving multi-point temperature sensors to measure the semiconductor wafer temperature and its distribution uniformity. A gold-plated reflector plate is attached to the bottom side of the lamp housing for reflecting and directing optical energy toward the wafer surface. The distance between the reflector plate and the wafer and the lamps and the wafer may be adjusted with the use of a spacial elevator and adaptor assembly. The multi-zone illuminator allows uniform wafer heating during both transient and steady-state wafer heating cycles.

摘要翻译： 描述了用于处理半导体晶片的多区域照明器，其包括嵌入在灯壳体的反射器侧中的多个源灯和虚拟灯。 源灯布置成多个同心圆形区域。 照明器还包括用于接收多点温度传感器以测量半导体晶片温度及其分布均匀性的多个光管。 一个镀金的反光板安装在灯壳的底部，用于将光能反射并引导到晶片表面。 可以使用空间电梯和适配器组件来调节反射板与晶片与灯和晶片之间的距离。 多区域照明器允许在瞬态和稳态晶片加热循环期间均匀的晶片加热。

公开(公告)号：US5326170A

公开(公告)日：1994-07-05

申请号：US115920

申请日：1993-09-01

申请人： Mehrdad M. Moslehi ,  Habib Najm ,  Lino A. Velo

发明人： Mehrdad M. Moslehi ,  Habib Najm ,  Lino A. Velo

IPC分类号： G01K15/00 ,  G01J5/00 ,  G01J5/52 ,  H01L21/26 ,  H01L21/324 ,  H01L21/66 ,  G01J5/54

CPC分类号： G01K15/005 ,  G01J5/522 ,  G01J2005/0048

摘要： A method for calibrating at least one temperature sensor. A wafer (30) having calibration structures of a material having a melting point in the range of 150.degree. to 1150.degree. C. is provided. The temperature sensor is operable to detect a temperature dependent characteristic of the wafer and output a signal corresponding to the temperature depending characteristic. The power input is selectively varied and the wafer temperature is ramped for a calibration run. A wafer characteristic, such as wafer reflectance, radiance, or emissivity, is monitored. A first step change in the wafer characteristic corresponding to a wafer temperature equal to the melting point of the calibration structures is detected and a set of calibration parameters for each temperature sensor being calibrated is calculated.

摘要翻译： 一种用于校准至少一个温度传感器的方法。 提供具有熔点在150〜1150℃范围内的材料的校准结构的晶片（30）。 温度传感器可操作以检测晶片的温度依赖特性并输出对应于温度依赖特性的信号。 功率输入有选择地变化，并且晶片温度斜坡进行校准运行。 监测诸如晶片反射率，辐射度或发射率的晶片特性。 检测对应于等于校准结构的熔点的晶片温度的晶片特性的第一阶跃变化，并计算正在校准的每个温度传感器的一组校准参数。

公开(公告)号：US5305417A

公开(公告)日：1994-04-19

申请号：US37771

申请日：1993-03-26

申请人： Habib N. Najm ,  Mehrdad M. Moslehi ,  Somnath Banerjee ,  Lino A. Velo

发明人： Habib N. Najm ,  Mehrdad M. Moslehi ,  Somnath Banerjee ,  Lino A. Velo

IPC分类号： G01J5/10 ,  C30B25/10 ,  G01J5/08 ,  G05D23/19 ,  G05D23/27 ,  H01L21/66 ,  G01J5/06

CPC分类号： B24B37/013 ,  C30B25/10 ,  G05D23/27 ,  H01L22/26 ,  H01L22/12

摘要： In a RTP reactor where wafer temperature is measured by a pyrometer assembly (32), a pyrometer assembly (50) is further provided to measure the temperature of the quartz window (30) that is situated between the wafer pyrometer assembly (32) and the wafer (16) that is being processed. During the calibration procedure (100, 120) where a thermocouple wafer is used, the measurements from the wafer pyrometer assembly (32) and the window pyrometer assembly (50) are calibrated, and pyrometer measurements and thermocouple measurements are collected and compiled into calibration tables. During actual RTP reactor operation, the data from the calibration tables and current wafer and window pyrometer measurements are used to compute corrected wafer temperature(s). The corrected wafer temperature(s) is/are then used to control the intensities of the heating lamps according to the wafer processing heating schedule.

摘要翻译： 在通过高温计组件（32）测量晶片温度的RTP反应器中，还提供高温计组件（50）以测量位于晶片高温计组件（32）和晶片高温计组件（32）之间的石英窗口（30）的温度， 正在处理的晶片（16）。 在使用热电偶晶片的校准过程（100,120）期间，对来自晶片高温计组件（32）和窗口高温计组件（50）的测量进行校准，并将高温计测量和热电偶测量值收集并编译成校准表 。 在实际的RTP电抗器操作期间，使用来自校准表和当前晶圆和窗口高温计测量的数据来计算校正的晶片温度。 然后使用校正的晶片温度来根据晶片加工时间表来控制加热灯的强度。

公开(公告)号：US5273609A

公开(公告)日：1993-12-28

申请号：US580986

申请日：1990-09-12

申请人： Mehrdad M. Moslehi

发明人： Mehrdad M. Moslehi

IPC分类号： C23C16/52 ,  H01J37/32 ,  H01L21/00 ,  H01L21/205 ,  H01L21/3065

CPC分类号： H01L21/67069 ,  C23C16/52 ,  H01J37/32357 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30655 ,  Y10S438/935

摘要： A multi-switch processing methodology and a multi-channel time-division plasma chopping device (10) for in-situ plasma-assisted semiconductor wafer processing associated with a plasma and/or photochemical processing equipment. The device (10) comprises a main transfer channel (72) associated with the processing reactor for transferring process gas and activated plasma mixtures into the reactor. A plurality of gas discharge channels (18, 22, 26, and 30) associate with the main transfer channel (72) for independently directing various gases and activated plasma combinations to main transfer channel (72). Process excitation sources (16, 20, 24 and 28) associate with at least one of said gas discharge or activation channels to independently and selectively activate process gases and to control gas activation and flow from the discharge channels to the main transfer channel (72). The method of the present invention performs multi-channel time-division plasma chopping by independently and selectively generating plasma or activated species using a plurality of remote plasma generation process energy sources (16, 20, 24, and 28) associated with the semiconductor wafer fabrication reactor.

摘要翻译： 一种用于与等离子体和/或光化学处理设备相关联的原位等离子体辅助半导体晶片处理的多开关处理方法和多通道时分等离子体斩波装置（10）。 装置（10）包括与处理反应器相关联的主转移通道（72），用于将处理气体和活化的等离子体混合物输送到反应器中。 多个气体排放通道（18,22,26和30）与主转移通道（72）相关联，用于独立地将各种气体和活化的等离子体组合引导到主转移通道（72）。 过程激励源（16,20,24和28）与所述气体排放或活化通道中的至少一个相关联以独立地和选择性地激活处理气体并且控制气体激活和从排出通道流向主传送通道（72） 。 本发明的方法通过使用与半导体晶片制造相关联的多个远程等离子体生成工艺能源（16,20,24和28）独立地和选择性地产生等离子体或活化物质来执行多通道时分等离子体斩波 反应堆。

公开(公告)号：US5268989A

公开(公告)日：1993-12-07

申请号：US870446

申请日：1992-04-16

申请人： Mehrdad M. Moslehi ,  Robert Matthews ,  Cecil J. Davis

发明人： Mehrdad M. Moslehi ,  Robert Matthews ,  Cecil J. Davis

IPC分类号： H01L21/26 ,  G01J5/00 ,  H01L21/00 ,  H01L21/324 ,  C23C16/48 ,  H05B3/00

CPC分类号： H01L21/67115

摘要： A multi-zone illuminator for processing semiconductor wafers comprises a plurality of source lamps and dummy lamps embedded in the reflector side of a lamp housing. The source lamps are arranged in a plurality of concentric circular zones. The illuminator also comprises plurality of light pipes for receiving multi-point temperature sensors to measure the semiconductor wafer temperature and its distribution uniformity. A gold-plated reflector plate is attached to the bottom side of the lamp housing for reflecting and directing optical energy toward the wafer surface. The distance between the reflector plate and the wafer and the lamps and the wafer may be adjusted with the use of a spacial elevator and adaptor assembly. The multi-zone illuminator allows uniform wafer heating during both transient and steady-state wafer heating cycles.

公开(公告)号：US5261965A

公开(公告)日：1993-11-16

申请号：US937232

申请日：1992-08-28

申请人： Mehrdad M. Moslehi

发明人： Mehrdad M. Moslehi

IPC分类号： B08B7/00 ,  H01L21/00 ,  H01L21/306 ,  B08B3/08 ,  B08B3/10 ,  B08B3/12

CPC分类号： H01L21/02046 ,  B08B7/0021 ,  B08B7/0035 ,  H01L21/02052 ,  H01L21/6704

摘要： A method and system for semiconductor wafer cleaning within a condensed-phase processing environment (54) is based on first cooling the semiconductor wafer (52) to a predetermined temperature in order to condense a liquid film (156) on the semiconductor wafer surface from a condensable process gas or gas mixture. Then, the method and system promote thermally activated surface reactions and rapidly evaporate liquid film (156) from the semiconductor wafer surface using a high peak power, short pulse duration energy source such as a pulsed microwave source to dissolve surface contaminants and produce drag forces sufficiently large to remove particulates (154) and other surface contaminants from the surface of the semiconductor wafer. The method and system of this invention can remove various organic, metallic, native oxide, and particulate contaminants from semiconductor wafer surface.

摘要翻译： 在冷凝相处理环境（54）内的半导体晶片清洗方法和系统基于将半导体晶片（52）首先冷却至预定温度，以便从半导体晶片表面上的液膜（156）从 可冷凝工艺气体或气体混合物。 然后，该方法和系统促进热激活的表面反应，并使用高峰值功率，短脉冲持续时间的能源（例如脉冲微波源）快速蒸发来自半导体晶片表面的液膜（156），以溶解表面污染物并充分产生拖曳力 较大以从半导体晶片的表面去除微粒（154）和其它表面污染物。 本发明的方法和系统可以从半导体晶片表面去除各种有机，金属，天然氧化物和微粒污染物。

公开(公告)号：US5219783A

公开(公告)日：1993-06-15

申请号：US856008

申请日：1992-03-20

申请人： Mehrdad M. Moslehi

发明人： Mehrdad M. Moslehi

IPC分类号： H01L21/324 ,  H01L21/033 ,  H01L21/22 ,  H01L21/225 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823892 ,  H01L21/0337 ,  H01L21/22 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/0928 ,  Y10S438/92

摘要： A method of forming doped well regions in a semiconductor layer 14 is disclosed herein. At least one n-doped region 30 and at least one p-doped region 36 are formed in the semiconductor layer 14. The n-doped region 30 is separated from the p-doped region 36 by a separation region 39. An oxide layer 32 (38), for example silicon dioxide, is formed over the n-doped region 30 and p-doped region (36) but not over the separation region 39. The semiconductor layer 14 is then heated (e.g., at a temperature of less than 1150.degree. C.) in a nitridizing environment such as ammonia. Other structures and methods are also disclosed.

公开(公告)号：US5184398A

公开(公告)日：1993-02-09

申请号：US752742

申请日：1991-08-30

申请人： Mehrdad M. Moslehi

发明人： Mehrdad M. Moslehi

IPC分类号： C23C16/458 ,  C23C16/52 ,  H01L21/66 ,  H01L21/683

CPC分类号： H01L21/6833 ,  C23C16/4583 ,  C23C16/52 ,  H01L21/6831 ,  H01L22/14 ,  H01L2924/0002 ,  Y10T279/23 ,  Y10T29/49117

摘要： A system 20 for measuring the sheet resistance of a conductive layer on the top surface of a semiconductor wafer 22 is disclosed herein. In one embodiment, the system includes a chuck 30 electrically coupled to the backside surface of the wafer 22. The chuck 30 is capable of supporting the wafer 22 electrostatically. A signal source 40 provides an excitation signal to the wafer 22 and circuitry for monitoring an induced signal is provided. The sheet resistance on the top surface of the wafer 22 is determined from the measurements of the excitation and induced electrical signals. Other systems and methods are also disclosed.

摘要翻译： 本文公开了一种用于测量半导体晶片22的顶表面上的导电层的薄层电阻的系统20。 在一个实施例中，系统包括电耦合到晶片22的背面的卡盘30.卡盘30能够静电地支撑晶片22。 信号源40向晶片22提供激励信号，并且提供用于监控感应信号的电路。 根据激发和感应电信号的测量来确定晶片22顶表面上的薄层电阻。 还公开了其它系统和方法。

公开(公告)号：US5073516A

公开(公告)日：1991-12-17

申请号：US662078

申请日：1991-02-28

申请人： Mehrdad M. Moslehi

发明人： Mehrdad M. Moslehi

IPC分类号： H01L21/20 ,  H01L21/762

CPC分类号： H01L21/76294 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/097

摘要： This is a method of fabricating a high-performance semiconductor device. The method comprises: forming a first insulating structure, preferably a layer of silicon nitride (e.g. region 24 in FIG. 2) on a layer of thermally grown oxide (e.g. region 22), on a substrate (e.g. region 20), preferably silicon; patterning and anisotropically etching the first insulating structure to expose a portion of the substrate and sidewalls of the first insulating structure; forming a second insulating structure, preferably a layer of oxide (e.g. region 28 in FIG. 3) on a layer of nitride (the bottom second insulating layer is preferably an etch-stop layer with respect to the removal of the top second insulating layer) (e.g. region 26 in FIG. 3), on the patterned first insulating structure, along the sidewalls of the first insulating structure, and on the exposed semiconductor substrate; anisotropically removing portions of the second insulating structure leaving a sidewall region of the second insulating structure (e.g. regions 30 and 32 in FIG. 4) along the sidewall of the first insulating structure and a region of the second insulating structure on a portion of the exposed substrate, and exposing a portion of the exposed substrate; forming a region of semiconducting material (e.g. regions 36 and 34, respectively, in FIG. 5), preferably a selectively grown semiconducting layer (preferably in-situ doped epitaxial silicon), encompassed by the second insulating structure and the exposed region of the substrate; sequentially and selectively etching the second insulating sidewall region to substantially expose the sidewalls of the selectively grown semiconducting region and top of the semiconducting region; and forming a third insulating layer (e.g. region 40 in FIG. 8 and region b 46 in FIG. 11), preferably a thermally grown oxide layer or a low-temperature plasma oxidation layer, on the exposed semiconducting region and on the exposed sidewalls of the semiconducting region.