公开(公告)号：US20150244364A1

公开(公告)日：2015-08-27

申请号：US14711538

申请日：2015-05-13

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/00 ,  G11C11/4093 ,  G11C11/419 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: A non-volatile memory device determines, based at least partly on a first multi-bit device address received via a signaling interface and an incoming chip-select signal, whether the device is to participate in a memory access transaction by receiving or outputting data via an I/O node of the signaling interface. Based at least in part on that determination, on-die termination circuitry within the non-volatile memory device switchably couples or decouples a termination resistance between the I/O node and a supply voltage node during a data transmission phase of the memory access transaction.

Abstract translation: 至少部分地基于经由信令接口和输入芯片选择信号接收到的第一多位设备地址来确定设备是否通过接收或输出数据来参与存储器访问事务，非易失性存储器设备 信令接口的I / O节点。 至少部分地基于该确定，在存储器访问事务的数据传输阶段期间，非易失性存储器件内的片上终端电路可切换地将I / O节点和电源电压节点之间的终端电阻耦合或去耦。

公开(公告)号：US20150084672A1

公开(公告)日：2015-03-26

申请号：US14560357

申请日：2014-12-04

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: G06F13/40 ,  H03K19/0175 ,  G11C11/4093

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.

Abstract translation: 集成电路装置向动态随机存取存储器（DRAM）发送指定DRAM内数字控制值的编程的一个或多个命令，数字控制值指示DRAM要耦合到DRAM的数据接口的终端阻抗 DRAM响应于接收到写入命令并且在接收与写入命令相对应的写入数据期间，并且DRAM在接收到与写入命令相对应的写入数据之后与数据接口分离。 此后，集成电路装置向DRAM发送指示在第一时间间隔期间通过DRAM的数据接口对写入数据进行采样的写入命令，并且使得DRAM在第一时间间隔期间将终止阻抗耦合到数据接口 时间间隔，并在第一个时间间隔后将数据接口的终端阻抗解耦。

公开(公告)号：US08981811B2

公开(公告)日：2015-03-17

申请号：US13952393

申请日：2013-07-26

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/0175 ,  G06F13/40 ,  G11C11/4093

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the two non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation. When outputting read data via the data I/O in a memory read operation, the memory device switchably couples to the data I/O at least a portion of the load elements included in the sets of load elements.

Abstract translation: 集成电路存储器件存储指定相应终端阻抗的多个数字值。 存储器件可将各组负载元件可切换地耦合到数据输入/输出（I / O），以施加由数字值指定的终端阻抗，包括在空闲状态期间向数据I / O施加第一终端阻抗 所述存储器件在所述存储器件在存储器写入操作中接收到写入数据并将所述两个不相等的终端阻抗中的第二个施加到所述数据I上时，将两个不相等的终端阻抗中的第一个施加到所述数据I / O / O，而另一个存储器件在存储器写入操作中接收写入数据。 当在存储器读取操作中经由数据I / O输出读取数据时，存储器件可切换地耦合到包含在负载元件组中的负载元件的至少一部分的数据I / O。

公开(公告)号：US20150042378A1

公开(公告)日：2015-02-12

申请号：US14523923

申请日：2014-10-26

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/0175 ,  G11C11/401 ,  H03K19/00

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.

Abstract translation: 在具有耦合到一个或多个集成电路存储器件的集成电路缓冲器件的存储器模块中，缓冲器件经由一组数据输入从外部控制部件接收写入数据信号，写入数据信号指示写入数据为 存储在一个或多个存储器件中。 缓冲装置内的逻辑基于从控制部件接收到的指示和缓冲装置的内部状态，顺序地在数据输入端施加可控终端阻抗配置，在第一内部的每个数据输入端施加第一可控终端阻抗配置 所述缓冲器装置的状态与所述数据输入上的所述写数据信号的接收相对应，以及在所述第一内部状态的所述缓冲器件的第二内部状态期间，在每个所述数据输入端施加第二可控终端阻抗配置。

公开(公告)号：US20140285232A1

公开(公告)日：2014-09-25

申请号：US14192550

申请日：2014-02-27

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh

IPC: H03K19/00

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

Abstract: Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.

Abstract translation: 描述的是第一集成电路（IC）中的通信系统通过单端通信信道与第二IC进行通信。 双向参考通道在第一和第二IC之间延伸并在两端终止。 参考通道每端的终端阻抗支持用于在不同方向上传送信号的不同模式。 可以针对每个信令方向优化参考信道的终止阻抗。

公开(公告)号：US20140258768A1

公开(公告)日：2014-09-11

申请号：US14351456

申请日：2012-10-11

Applicant: RAMBUS INC.

Inventor： Yu Chang ,  Lei Luo ,  Kyung Suk Oh

IPC: G06F1/32

CPC classification number: G06F1/32 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

Abstract: Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

Abstract translation: 公开的实施例涉及改变发射机和/或接收机设置以处理由诸如功率状态或时钟启动事件的改变等预定事件引起的可靠性问题的系统。 一个实施例在正常操作模式期间操作发射机时使用第一设置，以及在预定事件之后的过渡期间操作发射机时的第二设置。 第二实施例在接收机中使用类似的第一和第二设置，或在双向链路的一侧采用的发射机和接收机两者中。第一和第二设置可以与不同的摆动电压，边缘速率，均衡和/或阻抗相关联 。

公开(公告)号：US20140169438A1

公开(公告)日：2014-06-19

申请号：US14014047

申请日：2013-08-29

Applicant: Rambus Inc.

Inventor： Qi Lin ,  Brian Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Kyung Suk Oh ,  Jared L. Zerbe

IPC: H04L7/033 ,  H04L25/03

CPC classification number: H04L25/03254 ,  H04L7/0025 ,  H04L7/0054 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/03057 ,  H04L25/03885 ,  H04L43/028 ,  H04L2025/03617

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract translation: 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。