公开(公告)号：US09245840B2

公开(公告)日：2016-01-26

申请号：US14527293

申请日：2014-10-29

Applicant: Renesas Electronics Corporation

Inventor： Takasuke Hashimoto ,  Shinichi Uchida ,  Yasutaka Nakashiba ,  Takatsugu Nemoto

IPC: H01L23/552 ,  H01L23/522 ,  H01L23/58 ,  H05K9/00

CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L2924/0002 ,  H05K9/00 ,  H01L2924/00

Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor.An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

Abstract translation: 为了抑制由电感器引起的噪声泄漏到外部，并且还被配置为使得磁场强度变化到达电感器。 电感器在平面视图中围绕内部电路，并且还与内部电路电连接。 电感器的上侧由上屏蔽部分覆盖，电感器的下侧由下屏蔽部分覆盖。 上部屏蔽部分通过使用多层布线层形成。 上部屏蔽部分具有多个第一开口。 第一个开口在平面视图中与电感器重叠。

公开(公告)号：US08753922B2

公开(公告)日：2014-06-17

申请号：US13741910

申请日：2013-01-15

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba ,  Kenta Ogawa

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/48 ,  H01L23/522 ,  H01L23/64 ,  H01L23/544

CPC classification number: H01L23/5227 ,  H01L21/56 ,  H01L23/48 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/544 ,  H01L23/645 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2223/6655 ,  H01L2224/04042 ,  H01L2224/29 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract translation: 第一半导体芯片和第二半导体芯片在第一多层互连层和第二多层互连层彼此相对的方向上彼此重叠。 当在平面图中看到时，第一电感器和第二电感器重叠。 第一半导体芯片和第二半导体芯片具有不相对的非对置区域。 第一多层互连层在非对置区域中具有第一外部连接端子，并且第二多层互连层在非对置区域中具有第二外部连接端子。

公开(公告)号：US20140103487A1

公开(公告)日：2014-04-17

申请号：US14137839

申请日：2013-12-20

Applicant: Renesas Electronics Corporation

Inventor： Masayuki Furumiya ,  Yasutaka Nakashiba

IPC: H01L49/02

CPC classification number: H01L28/10 ,  G01R31/3025 ,  G01R31/315 ,  H01L22/14 ,  H01L23/544 ,  H01L24/06 ,  H01L2223/5446 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device, includes a first substrate having a main surface and a rear surface opposing to the main surface, a first circuit including a plurality of transistors formed over the main surface, a first insulating film formed over the main surface to cover the first circuit, a first inductor formed in the first insulating film over the main surface, the first inductor being electrically connected to the first circuit; and a bonding pad formed over the main surface, the bonding pad being located at a first area, the first inductor being located at a second area, the first area being different from the second area in a plan view, and a second substrate having a main surface, a rear surface opposing to the main surface and a second inductor formed over the main surface.

Abstract translation: 一种半导体器件，包括具有主表面和与主表面相对的后表面的第一衬底，包括形成在主表面上的多个晶体管的第一电路，形成在主表面上以覆盖第一电路的第一绝缘膜 形成在所述主表面上的所述第一绝缘膜中的第一电感器，所述第一电感器电连接到所述第一电路; 以及形成在所述主表面上的接合焊盘，所述接合焊盘位于第一区域处，所述第一电感器位于第二区域，所述第一区域在平面图中不同于所述第二区域，所述第二基板具有 主表面，与主表面相对的后表面和形成在主表面上的第二电感器。

公开(公告)号：US20130327838A1

公开(公告)日：2013-12-12

申请号：US13964446

申请日：2013-08-12

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba ,  Hiroaki Ohkubo ,  Mitsuji Okada ,  Shigeharu Nakata ,  Shuuichi Kagawa

IPC: G06K19/073 ,  H03K19/0175

CPC classification number: G06K19/073 ,  G11C7/24 ,  H03K19/017509

Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.

Abstract translation: 存储卡包括存储数据的存储器，发送从存储器接收的数据的驱动器以及将从驱动器接收的数据发送到设置在外部主单元中的接收器的至少一个发送器。 驱动器和至少一个发射器设置在单个IC（集成电路）芯片中，并且在平面图中不彼此重叠。

公开(公告)号：US20130056849A1

公开(公告)日：2013-03-07

申请号：US13667955

申请日：2012-11-02

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba

IPC: H01L27/08

CPC classification number: H01L23/5227 ,  H01L23/48 ,  H01L23/538 ,  H01L23/645 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor and a second spiral inductor formed in the multilayer interconnect, and an interconnect substrate formed over the semiconductor chip and having a third spiral inductor and a fourth spiral inductor. The third spiral inductor overlaps the first spiral inductor in a plan view. The fourth spiral inductor overlaps the second spiral inductor in the plan view. The third spiral inductor and the fourth spiral inductor collectively include a line, the line being spirally wound in a same direction in the third spiral inductor and the fourth spiral inductor.

Abstract translation: 半导体器件包括具有多层互连的半导体芯片，形成在多层互连中的第一螺旋电感器和第二螺旋电感器，以及形成在半导体芯片上并具有第三螺旋电感器和第四螺旋电感器的互连衬底。 第三螺旋电感器在平面图中与第一螺旋电感器重叠。 第四螺旋电感器在平面图中与第二螺旋电感器重叠。 第三螺旋电感器和第四螺旋电感器共同地包括线，该线在第三螺旋电感器和第四螺旋电感器中以相同的方向螺旋缠绕。

公开(公告)号：US11710695B2

公开(公告)日：2023-07-25

申请号：US16872848

申请日：2020-05-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/64 ,  H01L21/56 ,  H01L23/29 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5227 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/645 ,  H01L24/29

Abstract: A semiconductor device has a substrate, a first circuit, a first inductor, a second circuit and a second inductor IND2. The substrate includes a first region and a second region, which are regions different from each other. The first circuit is formed on the first region. The first inductor is electrically connected with the first circuit. The second circuit is formed on the second regions. The second inductor is electrically connected with the second circuit and formed to face the first inductor. A penetrating portion is formed in the substrate. The penetrating portion is formed such that the penetrating portion surrounds one or both of the first circuit and the second circuit in plan view.

公开(公告)号：US11562957B2

公开(公告)日：2023-01-24

申请号：US17190916

申请日：2021-03-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Kuwabara ,  Yasutaka Nakashiba

IPC: H01L23/522 ,  H01L23/64 ,  H01L23/31 ,  H01L23/495 ,  H01L21/762 ,  H01L21/74 ,  H01L49/02 ,  H01L21/56 ,  H01L21/8234 ,  H01L23/00

Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.

公开(公告)号：US11435645B2

公开(公告)日：2022-09-06

申请号：US16872805

申请日：2020-05-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02F1/225 ,  G02F1/21

Abstract: A semiconductor device has a first semiconducting layer including an optical waveguide, a dielectric layer formed on the optical waveguide, and a conductive layer formed on the dielectric layer. A refractive index of a material of the conductive layer is smaller than a refractive index of a material of the first semiconductor layer.

公开(公告)号：US11024566B2

公开(公告)日：2021-06-01

申请号：US16653127

申请日：2019-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Uchida ,  Akio Ono ,  Shinichi Kuwabara ,  Yasutaka Nakashiba

IPC: H01L23/495 ,  H01L23/522 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/64

Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.

公开(公告)号：US10991653B2

公开(公告)日：2021-04-27

申请号：US16438018

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Uchida ,  Yasutaka Nakashiba

IPC: H01L21/00 ,  H01L23/522 ,  H01L49/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L23/528 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.