公开(公告)号：US20140256116A1

公开(公告)日：2014-09-11

申请号：US14285718

申请日：2014-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC: H01L21/48 ,  H01L21/02

CPC classification number: H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

Abstract translation: 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US08729557B2

公开(公告)日：2014-05-20

申请号：US14027871

申请日：2013-09-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji Ono ,  Hideomi Suzawa ,  Tatsuya Arao

IPC: H01L27/14

CPC classification number: H01L27/1222 ,  G02F1/13624 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L33/08 ,  H01L33/62 ,  H01L2029/7863 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.

Abstract translation: 公开了一种电致发光器件，其具有衬底，衬底上的薄膜晶体管，薄膜晶体管上的绝缘膜，绝缘膜上的电致发光元件，电致发光元件上的钝化膜以及钝化膜上的对置衬底 。 电致发光元件被配置为通过对置基板发光，并且用填充物填充基板和对向基板之间的空间。 电致发光元件的特征在于薄膜晶体管的栅电极的锥形侧面。

公开(公告)号：US20130252385A1

公开(公告)日：2013-09-26

申请号：US13890293

申请日：2013-05-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC: H01L29/66

CPC classification number: H01L27/1296 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

公开(公告)号：US11949021B2

公开(公告)日：2024-04-02

申请号：US18133078

申请日：2023-04-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Hideomi Suzawa

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/146 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  H10B99/00

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H10B99/00 ,  H01L29/7854

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

公开(公告)号：US11901460B2

公开(公告)日：2024-02-13

申请号：US17708084

申请日：2022-03-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuta Endo ,  Hideomi Suzawa

IPC: H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H10B12/05 ,  H10B12/30

Abstract: A semiconductor device that can be highly integrated is provided.
The semiconductor device includes first and second transistors and first and second capacitors. Each of the first and second transistors includes a gate insulator and a gate electrode over an oxide. Each of the first and second capacitors includes a conductor, a dielectric over the conductor, and the oxide. The first and second transistors are provided between the first capacitor and the second capacitor. One of a source and a drain of the first transistor is also used as one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is also used as one electrode of the first capacitor. The other of the source and the drain of the second transistor is also used as one electrode of the second capacitor. The channel lengths of the first and second transistors are larger than the lengths in a direction parallel to short sides of fourth and fifth conductors.

公开(公告)号：US11437500B2

公开(公告)日：2022-09-06

申请号：US17167332

申请日：2021-02-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Masashi Tsubuku

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L27/146

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US11183516B2

公开(公告)日：2021-11-23

申请号：US16266263

申请日：2019-02-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hideomi Suzawa ,  Yuta Endo ,  Kazuya Hanaoka

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/475 ,  H01L21/4757

Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.

公开(公告)号：US10854636B2

公开(公告)日：2020-12-01

申请号：US15916860

申请日：2018-03-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji Ono ,  Hideomi Suzawa

IPC: H01L27/12 ,  C23F4/00 ,  H01L21/3213 ,  H01L21/768 ,  H01B1/02 ,  H01B5/14 ,  H01B13/00 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49

Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

公开(公告)号：US10522397B2

公开(公告)日：2019-12-31

申请号：US16354394

申请日：2019-03-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Hideomi Suzawa ,  Sachiaki Tezuka ,  Tetsuhiro Tanaka ,  Toshiya Endo ,  Mitsuhiro Ichijo

IPC: H01L21/768 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/423 ,  H01L29/49 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12

Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

公开(公告)号：US10411136B2

公开(公告)日：2019-09-10

申请号：US16126348

申请日：2018-09-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Hideomi Suzawa

IPC: H01L29/786 ,  H01L29/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/146 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.