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    Non-Volatile Memory Device Having a Memory Size
    93.
    发明申请
    Non-Volatile Memory Device Having a Memory Size 有权

    公开(公告)号：US20170090813A1

    公开(公告)日：2017-03-30

    申请号：US15053950

    申请日：2016-02-25

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G06F3/06

    CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0688 ,  G11C5/066 ,  G11C7/10 ,  G11C8/12

    Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.

    Method and system for managing a writing cycle of a data in a EEPROM memory cell
    94.
    发明授权
    Method and system for managing a writing cycle of a data in a EEPROM memory cell 有权
    用于管理EEPROM存储单元中数据写入周期的方法和系统

    公开(公告)号：US09576670B1

    公开(公告)日：2017-02-21

    申请号：US15244521

    申请日：2016-08-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

    Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

    Abstract translation: 在电可擦除可编程只读存储器类型的至少一个存储单元中写入至少一个数据的操作包括通过相应的擦除或编程脉冲擦除或编程单元的至少一个步骤。 通过在相应的擦除或编程步骤期间分析擦除或编程脉冲的形式来检查写入操作的正确或不正确的导通。 该分析的结果代表正在进行的写入操作正确或不正确。

    Method and System for Managing a Writing Cycle of a Data in a EEPROM Memory Cell
    95.
    发明申请
    Method and System for Managing a Writing Cycle of a Data in a EEPROM Memory Cell 审中-公开
    用于管理EEPROM存储单元中的数据写入周期的方法和系统

    公开(公告)号：US20170040060A1

    公开(公告)日：2017-02-09

    申请号：US15244521

    申请日：2016-08-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30

    CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

    Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

    Abstract translation: 用于在电可擦除和可编程只读存储器类型的至少一个存储单元中写入至少一个数据的操作包括通过相应的擦除或编程脉冲擦除或编程单元的至少一个步骤。 通过在相应的擦除或编程步骤期间对擦除或编程脉冲的形式的分析来检查写入操作的正确或不正确的导通。 该分析的结果代表正在进行的写入操作正确或不正确。

    Electronic device with a radiofrequency function
    96.
    发明授权
    Electronic device with a radiofrequency function 有权
    具有射频功能的电子设备

    公开(公告)号：US09544025B2

    公开(公告)日：2017-01-10

    申请号：US14849385

    申请日：2015-09-09

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: H04B5/00 ,  G06K19/077 ,  H02H9/04

    CPC classification number: H04B5/0037 ,  G06K19/07769 ,  H02H9/044

    Abstract: An electronic device includes at least one processing circuit connected through at least one terminal at a first reference voltage. At least one radio frequency communication circuit is connected at least to receive the reference voltage. At least one first pad is intended to be taken to a second reference voltage of at least one electronic circuit external to the device. At least one first resistive impedance is coupled between the terminal and the first pad.

    Abstract translation: 电子设备包括至少一个处理电路，其通过至少一个终端以第一参考电压连接。 至少一个射频通信电路至少连接以接收参考电压。 至少一个第一焊盘旨在被带到设备外部的至少一个电子电路的第二参考电压。 至少一个第一电阻阻抗耦合在端子和第一焊盘之间。

    Method and system for managing a writing cycle of a data in a EEPROM memory cell
    98.
    发明授权
    Method and system for managing a writing cycle of a data in a EEPROM memory cell 有权
    用于管理EEPROM存储单元中数据写入周期的方法和系统

    公开(公告)号：US09455034B1

    公开(公告)日：2016-09-27

    申请号：US15055552

    申请日：2016-02-27

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C16/06 ,  G11C13/00 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

    Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

    Abstract translation: 用于在电可擦除和可编程只读存储器类型的至少一个存储单元中写入至少一个数据的操作包括通过相应的擦除或编程脉冲擦除或编程单元的至少一个步骤。 通过在相应的擦除或编程步骤期间对擦除或编程脉冲的形式的分析来检查写入操作的正确或不正确的导通。 该分析的结果代表正在进行的写入操作正确或不正确。

    Integrated structure comprising neighboring transistors
    99.
    发明授权
    Integrated structure comprising neighboring transistors 有权
    包括相邻晶体管的集成结构

    公开(公告)号：US09431108B2

    公开(公告)日：2016-08-30

    申请号：US14657963

    申请日：2015-03-13

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Marc Battista ,  François Tailliet

    IPC: H01L29/49 ,  G11C16/04 ,  G11C11/412 ,  H01L27/11 ,  G11C11/418 ,  G11C16/08 ,  H01L27/088 ,  H01L29/51

    CPC classification number: H01L27/1104 ,  G11C11/4125 ,  G11C11/418 ,  G11C14/0063 ,  G11C16/045 ,  G11C16/08 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/513

    Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

    Abstract translation: 集成结构包括具有覆盖第一栅极电介质的第一可控栅极区域和与第一MOS晶体管相邻并具有覆盖第一栅极电介质的第二可控栅极区域的第一MOS晶体管的第一MOS晶体管。 公共导电区域覆盖第一和第二栅极区域并且由第二栅极电介质分离。 公共导电区域包括位于第一和第二栅极区域的一部分上的连续元件以及从连续元件向衬底延伸至第一栅极电介质的分支。 位于第一和第二栅极区之间的分支。

    Compact Memory Device of the EEPROM Type
    100.
    发明申请
    Compact Memory Device of the EEPROM Type 有权
    EEPROM类型的紧凑型存储器件

    公开(公告)号：US20160155506A1

    公开(公告)日：2016-06-02

    申请号：US14864354

    申请日：2015-09-24

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/14

    CPC classification number: G11C16/0483 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11534 ,  H01L29/7881

    Abstract: Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the t least one memory cell with a programming voltage split between a positive voltage and a negative voltage.

    Abstract translation: 集成的非易失性存储器件包括具有浮置栅极晶体管的EEPROM类型的集成存储器单元和串联连接在源极线和位线之间的选择晶体管，以及用于存储器单元的编程电路。 选择晶体管连接在浮栅晶体管和源极线之间。 编程电路被配置为用在正电压和负电压之间分配的编程电压来编程至少一个存储器单元。

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