公开(公告)号：US07345938B2

公开(公告)日：2008-03-18

申请号：US11797984

申请日：2007-05-09

申请人： Riichiro Takemura ,  Kiyoo Itoh ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Katsutaka Kimura

发明人： Riichiro Takemura ,  Kiyoo Itoh ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Katsutaka Kimura

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C5/025 ,  G11C5/14 ,  G11C7/06 ,  G11C7/08 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065 ,  H01L27/0207 ,  H01L27/10894

摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

摘要翻译： 一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。 用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。 使用网状电力线电路提供过驱动的可能性。 通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。 驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。

公开(公告)号：US20080002448A1

公开(公告)日：2008-01-03

申请号：US11896802

申请日：2007-09-06

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882

摘要： In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

摘要翻译： 在追求微型制造的大规模集成DRAM中，数据线字线耦合电容在配对数据线之间不平衡。 数据线字线的不平衡意味着当数据线经受放大时产生大的噪声，这极有可能引起数据线上非常小的信号的恶化和数据的错误放大。 连接到连接到一个数据线的多个存储单元的多个字线中的一个或几个字线交替地连接到布置在存储器阵列的相对侧上的子字驱动器阵列。 当数据线被放大时，正和负字线噪声分量在子字驱动器中彼此抵消，从而可以减小字线噪声。 因此，可以防止由读出放大器读出的信号劣化，从而提高存储器操作的可靠性。

公开(公告)号：US07262983B2

公开(公告)日：2007-08-28

申请号：US11652012

申请日：2007-01-11

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C5/02 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

公开(公告)号：US20070147152A1

公开(公告)日：2007-06-28

申请号：US11706409

申请日：2007-02-15

申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

公开(公告)号：US07184326B2

公开(公告)日：2007-02-27

申请号：US11268471

申请日：2005-11-08

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

公开(公告)号：US07098478B2

公开(公告)日：2006-08-29

申请号：US11168872

申请日：2005-06-29

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L29/72

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US20060126400A1

公开(公告)日：2006-06-15

申请号：US11349918

申请日：2006-02-09

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

IPC分类号： G11C7/10

CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882

摘要： In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

公开(公告)号：US20060034133A1

公开(公告)日：2006-02-16

申请号：US10534049

申请日：2002-11-08

申请人： Tomonori Sekiguchi ,  Shinichi Myatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Shinichi Myatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

公开(公告)号：US06990037B2

公开(公告)日：2006-01-24

申请号：US11048915

申请日：2005-02-03

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C8/00 ,  G11C7/02

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

公开(公告)号：US20050226069A1

公开(公告)日：2005-10-13

申请号：US11146119

申请日：2005-06-07

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4097

摘要： Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.

摘要翻译： 公开了一种读出放大器装置，其在DRAM中降低阵列电压时实现高速存取和缩短周期时间。 在用于在感测周期的早期阶段中分离阵列侧和读出放大器侧之间的数据线的TG时钟感测系统中，添加了恢复放大器RAP，其通过参考数据线中的数据来放大阵列侧的数据线 读出放大器，并且恢复放大器由比阵列电压VDL高的电压VDH驱动。 因此，TG时钟系统的高速感测操作与过驱动系统的高速恢复操作兼容，可以实现高速存取操作和缩短周期时间。