公开(公告)号：US08574992B2

公开(公告)日：2013-11-05

申请号：US13240568

申请日：2011-09-22

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L21/336 ,  G11C5/06

CPC classification number: H01L27/11206 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481

Abstract: A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.

Abstract translation: 描述了适用于低成本，高产量制造的用于三维（3D）存储器件的垂直互连架构。 用于3D存储器阵列的导电线（例如字线）和用于将阵列耦合到解码电路等的垂直连接器的接触焊盘形成为相同图案化材料层的部分。 可以使用相同的材​​料层通过使用单个掩模的蚀刻工艺形成接触焊盘和导电接入线。 通过与导电线同时形成接触焊盘，接触焊盘的图案化材料可以保护潜在的电路元件，否则在导电线图案化期间可能会损坏接触焊盘。

公开(公告)号：US20130264719A1

公开(公告)日：2013-10-10

申请号：US13443496

申请日：2012-04-10

Applicant: Shih-Hung Chen ,  Kuang-Yeu Hsieh ,  Cheng-Yuan Wang

Inventor： Shih-Hung Chen ,  Kuang-Yeu Hsieh ,  Cheng-Yuan Wang

IPC: H01L23/522 ,  H01L21/50

CPC classification number: H01L23/522 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0203 ,  H01L27/1052 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06177 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/73207 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/1443

Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.

Abstract translation: 半导体结构包括彼此组装的第一和第二芯片。 第一芯片包括N个第一导线，M个第二导线设置在第一导线上，N个第三导线垂直于第二导线并平行于第一导线，N个第一导通孔连接到第一导电 线，连接到第二导线的M组第二通孔，以及连接到第三导线的N组第三通孔。 第二和第一导电线形成重叠区域。 第三导线和N组第三通孔包括分别设置在重叠区域的第一和第三区域中的至少两个组。 M组第二通孔包括分别设置在重叠区域的第二区域和第四区域中的至少两个组。

公开(公告)号：US20130264683A1

公开(公告)日：2013-10-10

申请号：US13443417

申请日：2012-04-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC: H01L29/00 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基极，层叠结构和掺杂层。 堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和 第一侧壁的长边缘沿着通道方向延伸。 掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

公开(公告)号：US08536559B2

公开(公告)日：2013-09-17

申请号：US12498575

申请日：2009-07-07

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L29/06

CPC classification number: H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1293

Abstract: A phase change memory (PCM) is provided which includes a substrate, a plurality of bottom electrodes, a plurality of top electrodes, a plurality of phase change materials, and a plurality of thermal disturbance-preventing parts. The bottom electrodes are disposed in the substrate, and the top electrodes are disposed on the substrate. The phase change (PC) materials are disposed between the top and bottom electrodes, and each of the PC materials is conducted with one of the top electrodes and one of the bottom electrodes. The thermal disturbance-preventing parts are utilized to reduce the effect of thermal disturbance upon the PCM.

Abstract translation: 提供了一种相变存储器（PCM），其包括基板，多个底部电极，多个顶部电极，多个相变材料和多个热干扰防止部件。 底部电极设置在基板中，顶部电极设置在基板上。 相变（PC）材料设置在顶部和底部电极之间，并且每个PC材料都与一个顶部电极和一个底部电极一起导通。 利用热防干扰部件来减少热扰动对PCM的影响。

公开(公告)号：US20130075920A1

公开(公告)日：2013-03-28

申请号：US13240058

申请日：2011-09-22

Applicant: Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

Inventor： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

IPC: H01L23/48 ,  H01L21/283

CPC classification number: G11C5/04 ,  G11C5/06 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/0688 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

Abstract translation: IC器件包括一叠接触电平，每一层包括导电层和绝缘层。 电介质衬垫围绕接触层叠层内的开口内的层间导体。 开口穿过一叠接触层的一部分。 层间导体与通过电介质衬垫的每个接触层的导电层电绝缘。 开口处的导电层的一部分相对于相邻的绝缘层凹陷。 电介质衬垫可以具有在相邻绝缘层之间延伸的部分。

公开(公告)号：US20130075802A1

公开(公告)日：2013-03-28

申请号：US13240568

申请日：2011-09-22

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L27/085 ,  H01L21/28

CPC classification number: H01L27/11206 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481

Abstract: A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.

Abstract translation: 描述了适用于低成本，高产量制造的用于三维（3D）存储器件的垂直互连架构。 用于3D存储器阵列的导电线（例如字线）和用于将阵列耦合到解码电路等的垂直连接器的接触焊盘形成为相同图案化材料层的部分。 可以使用相同的材​​料层通过使用单个掩模的蚀刻工艺形成接触焊盘和导电接入线。 通过与导电线同时形成接触焊盘，接触焊盘的图案化材料可以保护潜在的电路元件，否则在导电线图案化期间可能会损坏接触焊盘。

公开(公告)号：US08383512B2

公开(公告)日：2013-02-26

申请号：US13114931

申请日：2011-05-24

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Abstract translation: 一种方法提供了用于3-D堆叠IC器件的互连区域的接触电平堆叠的电连接。 每个接触层包括导电层和绝缘层。 去除任何上层的一部分以露出第一接触层并为每个接触层产生接触开口。 使用一组N个掩模来蚀刻直到并包括2N个接触电平的接触开口。 每个掩模用于有效地蚀刻半个接触开口。 当N为3时，第一掩模蚀刻一个接触电平，第二掩模蚀刻两个接触电平，并且第三掩模蚀刻四个接触电平。 电介质层可以形成在接触开口的侧壁上。 电导体可以通过接触开口形成，其中电介质层将电导体与侧壁电绝缘。

公开(公告)号：US08344347B2

公开(公告)日：2013-01-01

申请号：US11611428

申请日：2006-12-15

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L47/00

CPC classification number: H01L45/144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: An electrode structure including two parallel electrical paths. A plurality of electrode layers, generally tabular in form is formed in a stack, the outermost layers providing electrical contacts, and defining a first electrical current path through the stack. Two sidewall conductor layers are formed to abut either end of the electrode layer stack, two sidewall conductor layers defining a second electrical current path. The ends of the sidewall conduction layers lie in the same planes as the electrode layer electrical contacts, such that electrode structure electrical contacts are each formed from one set of sidewall layer ends and an electrode layer electrical contact.

Abstract translation: 一种包括两个平行电路的电极结构。 多个电极层通常以叠片的形式形成在堆叠中，最外层提供电触点，并且限定穿过叠层的第一电流路径。 形成两个侧壁导体层以邻接电极层堆叠的任一端，限定第二电流路径的两个侧壁导体层。 侧壁导电层的端部位于与电极层电接触相同的平面中，使得电极结构电触头各自由一组侧壁层端部和电极层电接触形成。

公开(公告)号：US20120168955A1

公开(公告)日：2012-07-05

申请号：US12983832

申请日：2011-01-03

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L23/538 ,  H01L21/3205

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L27/11565 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Abstract translation: 集成电路图案包括具有X和Y方向部分的一组材料线。 X和Y方向部分具有第一和第二间距，第二间距比第一间距大至少3倍。 X方向部分是平行的，并且Y方向部分是平行的。 Y方向部分的端部区域包括主线部分和偏移部分。 偏移部分包括与主线部分间隔开并电连接到主线部分的偏移元件。 偏移部分限定用于后续图案转印过程的接触区域。 为了在集成电路处理过程中使用的多重图形化方法提供用于随后的图案转印过程的接触区域。

公开(公告)号：US08169761B2

公开(公告)日：2012-05-01

申请号：US12400799

申请日：2009-03-10

Applicant: Chih-Ting Yeh ,  Yung-Chih Liang ,  Shih-Hung Chen

Inventor： Chih-Ting Yeh ,  Yung-Chih Liang ,  Shih-Hung Chen

IPC: H02H9/00

CPC classification number: H03F1/523 ,  H01L27/0266 ,  H03F2200/441

Abstract: An ESD clamp circuit applied to a power amplifier is provided. The ESD clamp circuit includes a first line, a second line, a first circuit, a second circuit, an ESD detecting unit, a buffer unit, and an ESD clamp unit. The first line is coupled to the output terminal of the power amplifier. The first circuit is coupled to the first line. The second circuit is coupled to the first circuit. The ESD detecting unit is coupled to the first circuit and the second line. The buffer unit is coupled to the second circuit, the second line and the ESD detecting unit. The ESD clamp unit is coupled to the buffer unit, the first line and the second line. Therefore, at normal operation mode, the problem of signal loss caused by the leakage current of ESD clamp circuit can be avoided.

Abstract translation: 提供了应用于功率放大器的ESD钳位电路。 ESD钳位电路包括第一线，第二线，第一电路，第二电路，ESD检测单元，缓冲单元和ESD钳位单元。 第一行耦合到功率放大器的输出端。 第一电路耦合到第一线。 第二电路耦合到第一电路。 ESD检测单元耦合到第一电路和第二线。 缓冲单元耦合到第二电路，第二线路和ESD检测单元。 ESD钳位单元耦合到缓冲单元，第一线和第二线。 因此，在正常工作模式下，可以避免由ESD钳位电路的漏电流引起的信号损失问题。