公开(公告)号：US5943273A

公开(公告)日：1999-08-24

申请号：US899143

申请日：1997-07-23

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

公开(公告)号：US5844767A

公开(公告)日：1998-12-01

申请号：US675760

申请日：1996-07-03

申请人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H01L29/40 ,  G11C5/14 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0944 ,  G11C13/00

CPC分类号： G11C7/1078 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147

摘要： The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

摘要翻译： 电平转换电路包括第一电流切断电路，第二电流切断电路，电平移位电路和反相器。 第一电流切割电路包括连接到具有升压电位Vpp的节点的两个PMOS晶体管。 第二电流切断电路包括连接到接地节点的两个NMOS晶体管。 电平移位电路包括两个PMOS晶体管和两个NMOS晶体管。 在直流电流在具有升压电位Vpp的节点和接地节点之间流动之前，包括在第一电流切割电路中的任何晶体管和包括在第二电流切割电路中的任何晶体管都被截止。 因此，可以防止具有升压电位Vbb的节点与接地节点之间的电流。

公开(公告)号：US5828258A

公开(公告)日：1998-10-27

申请号：US639326

申请日：1996-04-25

申请人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G06F1/04 ,  G06F1/08 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

CPC分类号： G11C29/028 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401

摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.

公开(公告)号：US5748549A

公开(公告)日：1998-05-05

申请号：US735835

申请日：1996-10-23

申请人： Osamu Kometani ,  Shoichi Wakano ,  Mikio Asakura

发明人： Osamu Kometani ,  Shoichi Wakano ,  Mikio Asakura

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： A first interconnection frame is provided on a semiconductor substrate so as to surround a central circuit strip. A second interconnection frame is provided on first metal interconnection frame with an insulating film therebetween. Both ends of a supply line are in contact with second interconnection frame. There is a gap provided between both ends of a ground line and second interconnection frame. Ground line and first interconnection frame are connected, using a via hole provided in the insulating film. Thus, an improved dynamic random access memory in which the voltage levels of supply lines and ground lines are stabilized is provided.

摘要翻译： 第一互连框架设置在半导体衬底上，以围绕中央电路板。 第二互连框架设置在第一金属互连框架上，其间具有绝缘膜。 供应线的两端与第二互连框架接触。 在地线和第二互连框架的两端之间设置间隙。 使用设置在绝缘膜中的通孔连接接地线和第一互连框架。 因此，提供了其中电源线和接地线的电压电平稳定的改进的动态随机存取存储器。

公开(公告)号：US5726940A

公开(公告)日：1998-03-10

申请号：US833207

申请日：1997-04-14

申请人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani

发明人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50

CPC分类号： G11C29/46 ,  G11C29/34 ,  G11C29/50

摘要： In the semiconductor memory device in accordance with the present invention, when test mode is entered at WCbR+super V.sub.IH +address key timing, the test mode is terminated only at the WCbR+super V.sub.IH +address key timing. Therefore, when refresh is to be started in the test mode, erroneous entrance to another test mode can be prevented, ensuring highly reliable testing. Further, since it is not necessary to take into account the special condition to enter the refreshing operation in the test mode, formation of a test pattern is facilitated.

摘要翻译： 在根据本发明的半导体存储器件中，当以WCbR +超VIH +地址键定时输入测试模式时，测试模式仅在WCbR +超级VIH +地址键定时终止。 因此，当在测试模式下开始刷新时，可以防止对另一测试模式的错误进入，确保高度可靠的测试。 此外，由于不需要考虑在测试模式中进入刷新操作的特殊条件，因此便于形成测试图案。

公开(公告)号：US5708610A

公开(公告)日：1998-01-13

申请号：US602643

申请日：1996-02-16

申请人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

发明人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

IPC分类号： H01L21/8242 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L27/0288 ,  G11C11/4074 ,  G11C11/4076 ,  G11C5/14

摘要： For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply means only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.

摘要翻译： 对于包括在DRAM中的控制时钟信号和地址信号的每个焊盘，提供n型阱区，并且每个n型阱区仅通过第一较低电源线连接到上电源装置。 因此，与通过第二低电源线连接n个型阱的常规装置相比，减小了从p型阱中的电阻元件流向上部电源线的电流。 因此，可以防止对电阻元件8的损坏，并且DRAM的浪涌抗扰度增加。

公开(公告)号：US5687123A

公开(公告)日：1997-11-11

申请号：US312968

申请日：1994-09-30

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US5602793A

公开(公告)日：1997-02-11

申请号：US417527

申请日：1995-04-06

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potentials is generated to allow a stable supply of a power supply potential and a ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to a proximate operation power supply potential line and ground line through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带，以及以网状形状布置的多个操作电源电位线和多个接地电位线。 操作电源电位线和接地电位线包括与感测放大器频带平行并且接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到操作电源电位线和布置在感测放大器附近并与之并联的接地线。 驱动部件被设置用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 多个操作电源电位线和布置成网状的多个接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源电位和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的操作电源电位线和接地线，所以可靠且高速的感测操作是可能的，而与感测放大器驱动信号线的长度无关。

公开(公告)号：US5353427A

公开(公告)日：1994-10-04

申请号：US63487

申请日：1993-05-19

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC分类号： G06F12/08 ,  G11C7/10

CPC分类号： G06F12/0893 ,  G11C7/1021

摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

公开(公告)号：US5325336A

公开(公告)日：1994-06-28

申请号：US942320

申请日：1992-09-10

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band comprising a plurality of sense amplifiers, and a plurality of power supply and ground lines arranged in a meshed shape. Power supply and ground lines includes lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to a power supply and ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. Each drive component is provided for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of power supply and ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potential is generated to allow a stable supply of power supply and ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to proximate power supply and ground lines through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带以及以网状形状布置的多个电源和接地线。 电源和接地线包括与感测放大器频带平行并且接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到布置在感测放大器附近并与其平行布置的电源和接地线。 每个驱动部件被提供用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 布置成网状的多个电源和接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的电源和接地线，所以无论感测放大器驱动信号线的长度如何，都可以进行可靠且高速的感测操作。