公开(公告)号：US20080091907A1

公开(公告)日：2008-04-17

申请号：US11953803

申请日：2007-12-10

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarre ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarre ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.

摘要翻译： 集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。 指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

公开(公告)号：US20080064271A1

公开(公告)日：2008-03-13

申请号：US11901604

申请日：2007-09-17

申请人： Siew Hiew ,  Jim Ni ,  Abraham Ma ,  David Nguyen

发明人： Siew Hiew ,  Jim Ni ,  Abraham Ma ,  David Nguyen

IPC分类号： B23P19/04 ,  H01R13/502

CPC分类号： H01R13/6395 ,  H01R24/62 ,  Y10T29/49838

摘要： Embodiments of a plug and cap of a Universal-Serial-Bus (USB) device have been presented. In one embodiment, a USB device includes a main body, a piece of string, and a cap. The main body has a printed circuit board assembly (PCBA) and a casing, wherein the PCBA is partially housed in the casing, and the PCBA further includes a USB connector protruding out of the casing at a first end of the casing. The piece of string is coupled to the main body and the cap. The cap is detachably coupled to the first end of the casing of the main body to cover the USB connector, wherein the cap remains indirectly coupled to the casing via the piece of string when the cap is detached from the first end of the casing to expose the USB connector.

摘要翻译： 已经提出了通用串行总线（USB）设备的插头和盖的实施例。 在一个实施例中，USB设备包括主体，弦线和盖。 主体具有印刷电路板组件（PCBA）和壳体，其中PCBA部分地容纳在壳体中，并且PCBA还包括在壳体的第一端处从壳体突出的USB连接器。 琴弦连接到主体和帽上。 盖可拆卸地联接到主体的壳体的第一端以覆盖USB连接器，其中当帽从壳体的第一端分离以暴露时，盖保持通过弦线间接地联接到壳体 USB连接器。

公开(公告)号：US20070216800A1

公开(公告)日：2007-09-20

申请号：US11691406

申请日：2007-03-26

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： H04N7/01

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

摘要翻译： 存储器系统包括控制器芯片和耦合到控制器芯片的存储器模块。 信号线承载穿过信号线的信号，直到在信号线的末端达到终止。 时钟线承载穿过时钟线的时钟信号，以在时钟线的末端到达第二个终端。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件，并且在信号和时钟信号到达第一存储器件之后。

公开(公告)号：US07268602B2

公开(公告)日：2007-09-11

申请号：US10964737

申请日：2004-10-15

申请人： David Nguyen ,  Suresh Rajan

发明人： David Nguyen ,  Suresh Rajan

IPC分类号： H03L7/06

CPC分类号： G06F9/3869 ,  G06F1/06 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C11/401 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K5/135 ,  H03K5/1534

摘要： A method and apparatus for accommodating delay variations among multiple signals are provided. According to one embodiment of the invention, transitions of one or more of a plurality of lines between different levels are detected. The timing of a signal affecting recovery of information from the plurality of lines is adjusted according to the transitions detected. Examples of such a signal include one or more signals carried on one or more of the plurality of lines and a timing signal carried on a line separate from the plurality of lines.

摘要翻译： 提供一种用于适应多个信号之间的延迟变化的方法和装置。 根据本发明的一个实施例，检测不同级别之间的多条线路中的一条或多条线路的转变。 根据检测到的转变来调整影响来自多条线路的信息恢复的信号的定时。 这种信号的示例包括在多条线路中的一条或多条线路上承载的一个或多个信号以及与多条线路分离的线路上承载的定时信号。

公开(公告)号：US20070156943A1

公开(公告)日：2007-07-05

申请号：US11685152

申请日：2007-03-12

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： G06F13/14

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

摘要翻译： 存储器系统包括控制器芯片和耦合到控制器芯片的存储器模块。 信号线承载穿过信号线的信号，直到在信号线的末端达到终止。 时钟线承载穿过时钟线的时钟信号，以在时钟线的末端到达第二个终端。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件，并且在信号和时钟信号到达第一存储器件之后。

公开(公告)号：US20070147143A1

公开(公告)日：2007-06-28

申请号：US11681375

申请日：2007-03-02

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.

摘要翻译： 集成电路存储器件具有第一组引脚，以使用时钟信号接收行地址，后跟列地址。 器件具有第二组引脚，用于使用时钟信号接收检测命令和写入命令。 sense命令指定设备激活由行地址标识的一行存储器单元。 write命令指定存储器件接收写入数据，并将写入数据存储在由列地址标识的存储单元行中的位置。 在从第二组引脚接收写入命令的第一时间段开始第一个延迟之后，将写入命令内部发布到存储器件。 在从第一时间段开始第二延迟之后，在第三组引脚处接收写入数据。

公开(公告)号：US20050117240A1

公开(公告)日：2005-06-02

申请号：US10978644

申请日：2004-11-01

申请人： Raffi Codilian ,  William Johns ,  Charles Park ,  David Nguyen ,  Jack Chue

发明人： Raffi Codilian ,  William Johns ,  Charles Park ,  David Nguyen ,  Jack Chue

IPC分类号： G11B5/596 ,  G11B21/02 ,  G11B27/36 ,  H04R31/00

CPC分类号： G11B5/59633 ,  G11B5/59638 ,  Y10T29/49036

摘要： A method of manufacturing a disk drive and a disk drive where the width of the read element and the width of the write element are both measured at servo-writing time and the track pitch of the disk drive is set on the basis of those measurements. Disk drives with superior head width combinations are servo-written with a narrower track pitch in order to have a higher storage capacity. Disk drives with inferior head width combinations are detected before servo-writing so that the disk drive may be servo-written with wider track pitch rather than with a nominal track pitch that results in a subsequent drive failure during initial burn-in (IBI). The heads are used more efficiently in that heads that are more capable are used to their ability and less capable heads that would otherwise be disposed of are used at all.

摘要翻译： 基于这些测量，设置在伺服写入时刻测量读取元件的宽度和写入元件的宽度的盘驱动器和盘驱动器的方法，并且基于这些测量来设置磁盘驱动器的磁道间距。 具有优异头宽度组合的磁盘驱动器以较窄的磁道间距进行伺服写入，以具有更高的存储容量。 在伺服写入之前检测到具有较差头部宽度组合的磁盘驱动器，以便磁盘驱动器可以以更宽的磁道间距进行伺服写入，而不是在初始老化（IBI）期间导致后续驱动器故障的标称磁道间距。 头部被更有效地使用在那些使用能力更强的头部，否则将被处理的头部不太可用。

公开(公告)号：US20050079101A1

公开(公告)日：2005-04-14

申请号：US10682597

申请日：2003-10-09

申请人： Joel Dufresne ,  Bryan Feisel ,  Theresa Gerten ,  Brent Hansen ,  David Nguyen

发明人： Joel Dufresne ,  Bryan Feisel ,  Theresa Gerten ,  Brent Hansen ,  David Nguyen

IPC分类号： B01L3/00 ,  G01N31/22

CPC分类号： B01L3/502715 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/0812 ,  B01L2300/0816 ,  B01L2300/0864 ,  B01L2300/0887 ,  B01L2300/168 ,  G01N21/0303 ,  Y10S436/809 ,  Y10T156/1002 ,  Y10T156/1052 ,  Y10T156/1082

摘要： Sample processing devices that include transmissive layers and control layers to reduce or eliminate cross-talk between process chambers in the processing device are disclosed. The transmissive layers may transmit significant portions of signal light and/or interrogation light while the control layers block significant portions of signal light and/or interrogation light. Methods of manufacturing processing devices that include transmissive layers and control layers are also disclosed. The methods may involve continuous forming processes including co-extrusion of materials to form the transmissive layer and control layer in a processing device, followed by formation of the process chambers in the control layer. Alternatively, the methods may involve extrusion of materials for the control layer, followed by formation of process chambers in the control layer.

摘要翻译： 公开了包括透射层和控制层以减少或消除处理装置中的处理室之间的串扰的样品处理装置。 透射层可以传输信号光和/或询问光的大部分，同时控制层阻挡信号光和/或询问光的重要部分。 还公开了制造包括透射层和控制层的处理装置的方法。 所述方法可以包括连续的成形方法，包括共挤出材料以在处理装置中形成透射层和控制层，随后在控制层中形成处理室。 或者，所述方法可以包括挤出用于对照层的材料，随后在对照层中形成处理室。

公开(公告)号：US06571632B1

公开(公告)日：2003-06-03

申请号：US09573644

申请日：2000-05-18

申请人： Richard W. Browner ,  Richard L. Lemoine ,  Mark I. Jurras, III ,  David Nguyen ,  Robert Domnitz ,  Alan Robert Selfridge

发明人： Richard W. Browner ,  Richard L. Lemoine ,  Mark I. Jurras, III ,  David Nguyen ,  Robert Domnitz ,  Alan Robert Selfridge

IPC分类号： G01M1304

CPC分类号： G01L5/0009 ,  F16C19/52 ,  G01M13/04 ,  G01N2291/02845

摘要： An acoustic signal unit comprises a signal generation unit to generate a first electrical signal, a first transducer to generate an acoustic signal in response to the first electrical signal, and a second transducer to generate a second electrical signal in response to the received acoustic signal. A calculation unit is provided to compare the first and second electrical signals to determine the time of flight of the acoustic signal, wherein the time of flight corresponds to the stress in the rolling element bearing. The stress may be calculated according to a formula or by multiplying an acoustic time constant for the rolling element bearing by the distance traveled by the acoustic signal across the rolling element bearing, and by the time of flight determined by said comparison unit.

摘要翻译： 声信号单元包括产生第一电信号的信号产生单元，响应于第一电信号产生声信号的第一换能器，以及响应于所接收的声信号产生第二电信号的第二换能器。 提供计算单元以比较第一和第二电信号以确定声信号的飞行时间，其中飞行时间对应于滚动元件轴承中的应力。 可以根据公式计算应力，或者通过将滚动元件轴承的声学时间常数乘以由声学信号穿过滚动元件轴承所经过的距离乘以由所述比较单元确定的飞行时间来计算。

公开(公告)号：US06266730B1

公开(公告)日：2001-07-24

申请号：US09507303

申请日：2000-02-18

申请人： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

发明人： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

IPC分类号： H05K102

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

摘要翻译： 尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。 高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。 第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。 高频总线系统还包括没有与其连接的设备的第二总线段。 第二总线段还具有用于传播高频信号的至少一对传输线。 第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个 设备在大致相同的时间连接到第一总线段。 而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。 尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间 或控制，由信号携带。