公开(公告)号：US06627919B2

公开(公告)日：2003-09-30

申请号：US10319312

申请日：2002-12-12

申请人： Jer-shen Maa ,  Douglas James Tweet ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas James Tweet ,  Sheng Teng Hsu

IPC分类号： H01L2976

CPC分类号： H01L21/28525 ,  H01L21/28518 ,  H01L29/45

摘要： A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.

公开(公告)号：US06586260B2

公开(公告)日：2003-07-01

申请号：US09820078

申请日：2001-03-28

申请人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L28/65 ,  C23C16/40 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L28/75 ,  Y10T428/24917 ,  Y10T428/2495

摘要： A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness. An integrated circuit includes a substrate; an electrode deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir—Ta—O, Ir—Ti—O, Ir—Nb—O, Ir—Al—O, Ir—Hf—O, Ir—V—O, Ir—Zr—O and Ir—O; and a single-phase, c-axis PGO ferroelectric thin film formed on the electrode, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

公开(公告)号：US06534871B2

公开(公告)日：2003-03-18

申请号：US09855391

申请日：2001-05-14

申请人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2348

CPC分类号： H01L21/28518 ,  H01L29/456

摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

公开(公告)号：US06462366B1

公开(公告)日：2002-10-08

申请号：US09481674

申请日：2000-01-12

申请人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L2976

CPC分类号： H01L29/6684 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of &dgr;, includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p-well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2&dgr;; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p-well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2≧L1+2&dgr;, wherein &dgr; is the alignment tolerance of the lithographic process.

摘要翻译： 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> = L1 + 2delta; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对所述结构进行金属化。铁电存储晶体管包括其中形成有p阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> = L1 + 2delta，其中Δ是光刻工艺的对准公差。

公开(公告)号：US06372034B1

公开(公告)日：2002-04-16

申请号：US09687827

申请日：2000-10-12

申请人： Wei-Wei Zhuang ,  Jer-shen Maa ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Jer-shen Maa ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2122

CPC分类号： H01L21/31691

摘要： A method of preparing a PGO solution for spin coating includes preparing a 2-methoxyethanol organic solvent; adding Pb(OCH3CO)2.3H2O to the organic solvent at ambient temperature and pressure in a nitrogen-filled glaved box to form Pb in methoxyethanol; refluxing the solution in a nitrogen atmosphere at 150° C. for at least two hours; fractionally distilling the refluxed solution at approximately 150° C. to remove all of the water from the solution; cooling the solution to room temperature; determining the Pb concentration of the solution; adding the 2-methoxyethanol solution to the Pb 2-methoxyethanol until a desired Pb concentration is achieved; combining Ge(OR)4, where R is taken the group of Rs consisting of CH2CH3 and CH(CH3)2, and 2-methoxyethanol; and adding Ge(OR)4 2-methoxyethanol to PbO 2-methoxyethanol to form the PGO solution having a predetermined metal ion concentration and a predetermined Pb:Ge molar ration.

摘要翻译： 制备用于旋涂的PGO溶液的方法包括制备2-甲氧基乙醇有机溶剂; 在环境温度和压力下，在氮气充填的玻璃箱中加入Pb（OCH 3 CO）2.3H 2 O至有机溶剂中以在甲氧基乙醇中形成Pb; 将溶液在氮气气氛中在150℃下回流至少2小时; 在大约150℃下将回流的溶液分馏，以从溶液中除去所有的水; 将溶液冷却至室温; 测定溶液的Pb浓度; 将2-甲氧基乙醇溶液加入到Pb 2-甲氧基乙醇中直到达到所需的Pb浓度; 组合Ge（OR）4，其中R是由CH 2 CH 3和CH（CH 3）2组成的基团和2-甲氧基乙醇; 并向PbO 2 - 甲氧基乙醇中加入Ge（OR）4 2-甲氧基乙醇以形成具有预定的金属离子浓度和预定的Pb:Ge摩尔比的PGO溶液。

公开(公告)号：US06368960B1

公开(公告)日：2002-04-09

申请号：US09113667

申请日：1998-07-10

申请人： Sheng Teng Hsu ,  Jer-Shen Maa

发明人： Sheng Teng Hsu ,  Jer-Shen Maa

IPC分类号： H01L21336

CPC分类号： H01L29/66757 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

摘要： A method of forming a silicided device includes preparing a substrate by forming device areas thereon; providing structures that are located between the substrate and any silicide layers; forming a first layer of a first reactive material over the formed structures; providing insulating regions in selected portions of the structure; forming a second layer of a second reactive material over the insulating regions and the first layer of first reactive material; reacting the first and second reactive materials to form silicide layers; removing any un-reacted reactive material; forming structures that are located on the silicide layers; and metallizing the device.

摘要翻译： 一种形成硅化器件的方法包括通过在其上形成器件区域来制备衬底; 提供位于衬底和任何硅化物层之间的结构; 在所形成的结构上形成第一反应性材料的第一层; 在结构的选定部分提供绝缘区域; 在所述绝缘区域和所述第一反应性材料层上形成第二反应性材料层; 使第一和第二反应性材料反应形成硅化物层; 去除任何未反应的反应性材料; 形成位于硅化物层上的结构; 并对该装置进行金属化。

公开(公告)号：US06236113B1

公开(公告)日：2001-05-22

申请号：US09263970

申请日：1999-03-05

申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L213205

CPC分类号： H01L28/75 ,  H01L21/28291 ,  H01L28/55 ,  H01L29/516

摘要： An Ir combination film has been provided that is useful in forming an electrode of a ferroelectric capacitor. The combination film includes tantalum and oxygen, as well as iridium. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying Ta or TaN layer, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. A method for forming an Ir composite film barrier layer and Ir composite film ferroelectric electrode are also provided.

摘要翻译： 已经提供了可用于形成铁电电容器的电极的Ir组合膜。 组合膜包括钽和氧，以及铱。 Ir组合膜有效防止氧气扩散，并且在氧气环境中耐高温退火。 当与下面的Ta或TaN层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 还提供了形成Ir复合膜阻挡层和Ir复合膜铁电电极的方法。

公开(公告)号：US6018171A

公开(公告)日：2000-01-25

申请号：US834499

申请日：1997-04-04

申请人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien-Hsiung Peng

发明人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien-Hsiung Peng

IPC分类号： G11C11/22 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L29/78 ,  H01L21/8242

CPC分类号： G11C11/22 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391 ,  G11C11/223 ,  Y10S438/957

摘要： A method of forming the FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel, which extends into the drain junction region. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region. Formation of the various conductive channels may take place at various stages of the manufacture, depending on what other devices are built on the substrate, and depending on the efficiencies of the various orders of construction. The structure of the FEM cell semiconductor includes a substrate, which may be a bulk silicon substrate or an SOI-type substrate. Conductive channels of two types are located above the substrate.

摘要翻译： 形成FEM单元半导体结构的方法包括在硅衬底上形成用于铁电存储器（FEM）栅极单元的器件区域。 将合适的杂质注入器件区域以形成导电沟道，用作源极结区域，栅极结区域和漏极结区域。 FEM单元包括形成在基板上的FEM门单元。 在FEM栅极单元器件区域上的FEM栅极单元的源极连接区域和漏极结区域之间形成栅极结区域，该FEM栅极单元包括下部金属层，铁电（FE）层和上部金属 层。 在FEM栅极单元和栅极结区域之间形成浅接合层，作为延伸到漏极结区域的另一个导电沟道。 有限元门单元与源极区和漏极区间隔开，也就是FEM门单元和栅极结区之间的导电沟道。 各种导电通道的形成可以在制造的各个阶段进行，这取决于衬底上构建的其它器件，以及各种施工顺序的效率。 FEM单元半导体的结构包括可以是体硅基板或SOI型基板的基板。 两种类型的导电通道位于基板上方。

公开(公告)号：US06242771B1

公开(公告)日：2001-06-05

申请号：US09291688

申请日：1999-04-13

申请人： Sheng Teng Hsu ,  Chien Hsiung Peng ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Chien Hsiung Peng ,  Jong Jan Lee

IPC分类号： H01L29788

CPC分类号： H01L28/55 ,  C23C16/40 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/78391

摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb5Ge3O11 FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb5Ge3O11 FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.

摘要翻译： 在单晶硅的衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括：形成用于FEM门单元的硅器件区域; 处理器件区域以形成源极，栅极和漏极区域; 在所述栅极结区域上沉积FEM栅极单元，包括沉积下电极，通过化学气相沉积（CVD）沉积c轴取向的Pb5Ge3O11FE层，以及沉积上电极; 以及围绕所述FEM门单元沉积绝缘结构。 铁电存储器（FEM）单元包括：单晶硅衬底，其包括其中具有源极，栅极和漏极区域的有源区; 包括下电极，由CVD形成的c轴取向Pb5Ge3O11FE层和上电极的有限元门单元; 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，栅极和漏极。

公开(公告)号：US6011285A

公开(公告)日：2000-01-04

申请号：US2364

申请日：1998-01-02

申请人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien Hsiung Peng

发明人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien Hsiung Peng

IPC分类号： H01L21/8247 ,  C23C16/40 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L28/55 ,  C23C16/40 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/78391

摘要： The structure of a c-axis FEM cell semiconductor includes a silicon substrate; a source junction region and a drain junction region located in the substrate; a gate junction region located between the source junction region and the drain junction region; a FEM gate unit including a lower electrode, a c-axis oriented Pb.sub.5 Ge.sub.3 O.sub.11 FE layer and an upper electrode; wherein the FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and source, drain and gate electrodes.

摘要翻译： c轴FEM单元半导体的结构包括硅衬底; 源极结区域和位于衬底中的漏极结区域; 位于源极结区域和漏极结区域之间的栅极结区域; 包括下电极，c轴取向Pb5Ge3O11FE层和上电极的FEM门单元; 其中所述FEM门单元的尺寸设置在所述栅极结区域上，使得所述FEM栅极单元的任何边缘距离源极结区域和漏极结区域的边缘为距离“D” 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，漏极和栅极。