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公开(公告)号：US20210066579A1
公开(公告)日：2021-03-04
申请号：US16589083
申请日：2019-09-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US10930839B2
公开(公告)日：2021-02-23
申请号：US16739060
申请日：2020-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Jian-Cheng Chen , Yu-Ping Wang , Yu-Ruei Chen
Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.
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公开(公告)号：US20210020828A1
公开(公告)日：2021-01-21
申请号：US16531129
申请日：2019-08-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号：US20200373478A1
公开(公告)日：2020-11-26
申请号：US16438480
申请日：2019-06-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
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公开(公告)号：US20200176510A1
公开(公告)日：2020-06-04
申请号：US16214127
申请日：2018-12-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Hung-Chan Lin , Jing-Yin Jhang , Yu-Ping Wang
IPC: H01L27/22 , G11C11/16 , H01L23/48 , H01L23/485 , H01L23/544 , H01L21/321 , H01L21/762 , H01L43/12
Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.
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Patent Agency Ranking
公开(公告)号：US10290723B2
公开(公告)日：2019-05-14
申请号：US15981913
申请日：2018-05-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Tsen Lu , Chien-Ming Lai , Lu-Sheng Chou , Ya-Huei Tsai , Ching-Hsiang Chiu , Yu-Tung Hsiao , Chen-Ming Huang , Kun-Ju Li , Yu-Ping Wang
Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
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公开(公告)号：US20180269308A1
公开(公告)日：2018-09-20
申请号：US15981913
申请日：2018-05-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Tsen Lu , Chien-Ming Lai , Lu-Sheng Chou , Ya-Huei Tsai , Ching-Hsiang Chiu , Yu-Tung Hsiao , Chen-Ming Huang , Kun-Ju Li , Yu-Ping Wang
CPC classification number: H01L29/66545 , B32B1/00 , B32B18/00 , C22C32/0068 , H01L21/28088 , H01L29/4238 , H01L29/4966 , H01L29/511
Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
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公开(公告)号：US09711646B2
公开(公告)日：2017-07-18
申请号：US14230223
申请日：2014-03-31
Applicant: United Microelectronics Corp.
Inventor： Yu-Ping Wang , Jyh-Shyang Jenq , Yu-Hsiang Lin , Hsuan-Hsu Chen , Chien-Hao Chen , Yi-Han Ye
CPC classification number: H01L29/785 , H01L29/66795
Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.
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公开(公告)号：US20160104786A1
公开(公告)日：2016-04-14
申请号：US14543914
申请日：2014-11-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Yang , Yu-Feng Liu , Jian-Cun Ke , Chia-Fu Hsu , En-Chiuan Liou , Ssu-I Fu , Chi-Mao Hsu , Nien-Ting Ho , Yu-Ru Yang , Yu-Ping Wang , Chien-Ming Lai , Yi-Wen Chen , Yu-Ting Tseng , Ya-Huei Tsai , Chien-Chung Huang , Tsung-Yin Hsieh , Hung-Yi Wu
IPC: H01L29/49 , H01L27/092 , H01L21/28 , H01L21/321 , H01L27/088 , H01L21/8234
CPC classification number: H01L29/4966 , H01L21/28088 , H01L21/321 , H01L21/823431 , H01L21/82345 , H01L27/088 , H01L29/517 , H01L29/66545
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。
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公开(公告)号：US20250107454A1
公开(公告)日：2025-03-27
申请号：US18976359
申请日：2024-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
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