中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

179 records (took 0.022 seconds)

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    94.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 有权
    形成半导体结构的方法

    公开(公告)号：US20160276157A1

    公开(公告)日：2016-09-22

    申请号：US15169472

    申请日：2016-05-31

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Hsien Lin ,  Min-Hsien Chen

    IPC: H01L21/28 ,  H01L29/66 ,  H01L21/285

    CPC classification number: H01L21/28088 ,  H01L21/2855 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

    Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供其上具有介电层的基板。 电介质层在其中具有栅极沟槽，栅极电介质层形成在栅极沟槽的底部。 工作功能金属层和顶部阻挡层依次形成在栅极沟槽中。 对顶部阻挡层进行处理以形成含硅顶部阻挡层。 在栅极沟槽中形成低电阻率金属层。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    95.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20160035854A1

    公开(公告)日：2016-02-04

    申请号：US14881162

    申请日：2015-10-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

    IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

    Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

    Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

    Metal oxide semiconductor transistor and manufacturing method thereof
    96.
    发明授权
    Metal oxide semiconductor transistor and manufacturing method thereof 有权
    金属氧化物半导体晶体管及其制造方法

    公开(公告)号：US09219140B2

    公开(公告)日：2015-12-22

    申请号：US14592872

    申请日：2015-01-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Tai Chiang ,  Chun-Hsien Lin

    IPC: H01L29/76 ,  H01L29/78 ,  H01L21/285 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/768

    CPC classification number: H01L21/28518 ,  H01L21/28008 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/41725 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

    Abstract: The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

    Abstract translation: 本发明提供一种MOS晶体管，其包括衬底，栅极氧化物，栅极，源极/漏极区域和硅化物层。 栅极氧化物设置在衬底上，并且栅极设置在栅极氧化物上。 源极/漏极区域设置在栅极两侧的衬底中。 硅化物层设置在源极/漏极区域上，其中硅化物层包括弯曲的底部表面和弯曲的顶部表面，弯曲的顶部表面和弯曲的底部表面都朝向衬底弯曲，并且弯曲的顶部表面从两个凹陷 侧面，硅化物层尖端的两端在源极/漏极区域上升起，中间的硅化物层比外围的硅化物层厚，从而形成新月形结构。 本发明还提供一种MOS晶体管的制造方法。

    Method of forming shallow trench isolation structure
    97.
    发明授权
    Method of forming shallow trench isolation structure 有权
    形成浅沟槽隔离结构的方法

    公开(公告)号：US09105685B2

    公开(公告)日：2015-08-11

    申请号：US13941208

    申请日：2013-07-12

    Applicant: United Microelectronics Corp.

    Inventor： Chien-Ting Lin ,  Shih-Hung Tsai ,  Chun-Hsien Lin

    IPC: H01L21/762 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/8234

    CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845

    Abstract: A method of forming a shallow trench isolation structure is disclosed. Hard mask patterns are formed on a substrate. A portion of the substrate is removed, using the hard mask patterns as a mask, to form first trenches in the substrate, wherein a fin is disposed between the neighboring first trenches. A filling layer is formed in the first trenches. A patterned mask layer is formed on the filling layer. A portion of the filling layer and a portion of the fins are removed, using the patterned mask layer as a mask, to form second trenches in the substrate. A first insulating layer is formed on the substrate filling in the second trenches.

    Abstract translation: 公开了形成浅沟槽隔离结构的方法。 在基板上形成硬掩模图案。 使用硬掩模图案作为掩模去除衬底的一部分，以在衬底中形成第一沟槽，其中翅片设置在相邻的第一沟槽之间。 在第一沟槽中形成填充层。 在填充层上形成图案化掩模层。 使用图案化掩模层作为掩模，去除填充层的一部分和散热片的一部分，以在衬底中形成第二沟槽。 在填充在第二沟槽中的衬底上形成第一绝缘层。

    Semiconductor device having metal gate and manufacturing method thereof
    98.
    发明授权
    Semiconductor device having metal gate and manufacturing method thereof 有权
    具有金属栅极的半导体器件及其制造方法

    公开(公告)号：US08999830B2

    公开(公告)日：2015-04-07

    申请号：US14135520

    申请日：2013-12-19

    Applicant: United Microelectronics Corp.

    Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

    IPC: H01L21/3205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

    Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

Patent Agency Ranking