公开(公告)号：US08791011B2

公开(公告)日：2014-07-29

申请号：US13775983

申请日：2013-02-25

申请人： Yung-Chi Lin ,  Weng-Jin Wu ,  Shau-Lin Shue

发明人： Yung-Chi Lin ,  Weng-Jin Wu ,  Shau-Lin Shue

IPC分类号： H01L21/4763

CPC分类号： H01L21/76871 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

摘要： In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.

摘要翻译： 在此过程中，形成从半导体衬底的前表面延伸穿过半导体衬底的一部分的开口。 金属种子层形成在开口的侧壁上。 仅在金属种子层的一部分上形成阻挡层。 在阻挡层和金属种子层上形成金属层以填充开口。

公开(公告)号：US09418876B2

公开(公告)日：2016-08-16

申请号：US13224575

申请日：2011-09-02

申请人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81

摘要： A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

摘要翻译： 制造三维集成电路的方法包括将晶片附着到载体上，将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层，将晶片堆叠连接到胶带框架上，并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US08722540B2

公开(公告)日：2014-05-13

申请号：US12841874

申请日：2010-07-22

申请人： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

发明人： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834

摘要： A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.

摘要翻译： 一种方法包括通过粘合剂将晶片接合在载体上，并在晶片上进行稀化处理。 在进行稀化处理的步骤之后，去除未被晶片覆盖的粘合剂的一部分，同时由晶片覆盖的粘合剂部分未被除去。

公开(公告)号：US20130056865A1

公开(公告)日：2013-03-07

申请号：US13224575

申请日：2011-09-02

申请人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/78 ,  H01L23/498

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81

摘要： A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

摘要翻译： 制造三维集成电路的方法包括将晶片附着到载体上，将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层，将晶片堆叠连接到胶带框架上，并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US06511235B2

公开(公告)日：2003-01-28

申请号：US09745152

申请日：2000-12-19

申请人： Weng-Jin Wu ,  Yih-Der Guo ,  Tsung-Hsuan Chiu ,  Rong-Heng Yuang ,  Mu-Tao Chu

发明人： Weng-Jin Wu ,  Yih-Der Guo ,  Tsung-Hsuan Chiu ,  Rong-Heng Yuang ,  Mu-Tao Chu

IPC分类号： G02B636

CPC分类号： G02B6/4214 ,  G02B6/423 ,  G02B6/4232 ,  G02B6/4249

摘要： The present invention pertains to an integrated surface-emitting optoelectronic module and the method for making the same. The yellow light procedure is performed to define a V-groove width for disposing an optical fiber on a silicon substrate. After dry etching a vertical groove, a dielectric layer is grown on the surface of the silicon substrate to protect the vertical wall, preventing the groove from getting wider due to subsequent wet etching. A 45-degree mirror surface is formed so that an optoelectronic device can be disposed on the mirror surface in the flip chip method. The optoelectronic module employs a complete silicon substrate to assemble a surface-emitting optoelectronic devices and an optical fiber by passive alignment, and therefore can be free from misalignment due to separate assembly.

公开(公告)号：US20130075892A1

公开(公告)日：2013-03-28

申请号：US13246553

申请日：2011-09-27

申请人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/48 ,  H01L21/6835 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

摘要翻译： 一种用于制造三维集成电路的方法包括：提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠，在第一半导体管芯的第一侧上形成模塑料层，其中多个半导体管芯被嵌入 在模塑料层中。 该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出，将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US20120021604A1

公开(公告)日：2012-01-26

申请号：US12841874

申请日：2010-07-22

申请人： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

发明人： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

IPC分类号： H01L21/306 ,  H01L21/302 ,  H01L21/3065

CPC分类号： H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834

摘要： A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.

摘要翻译： 一种方法包括通过粘合剂将晶片接合在载体上，并在晶片上进行稀化处理。 在进行稀化处理的步骤之后，去除未被晶片覆盖的粘合剂的一部分，同时由晶片覆盖的粘合剂部分未被除去。