公开(公告)号：US06420751B1

公开(公告)日：2002-07-16

申请号：US09640880

申请日：2000-08-18

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Hirotada Kuriyama ,  Shigeto Maegawa

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Hirotada Kuriyama ,  Shigeto Maegawa

IPC分类号： H01L2976

CPC分类号： H01L27/092 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/7827

摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.

摘要翻译： 可以获得占据小面积的场效应晶体管和使用其的半导体器件。 栅电极设置在基板上，源极区域之间插入有第一层间绝缘膜。 栅电极被第二层间绝缘膜覆盖。 提供用于暴露源区域的一部分表面的接触孔，以穿透第一层间绝缘膜，栅电极和第二层间绝缘膜。 接触孔的侧壁表面被栅极绝缘膜覆盖。 第一导电类型的第一半导体层设置在与其接触的源极区域的表面上，直到栅电极的下表面。 沟道半导体层设置在第一半导体层的表面上直到栅电极的上表面。 在沟道半导体层上设置有用作漏极区的第一导电类型的第二半导体层。

公开(公告)号：US06351014B2

公开(公告)日：2002-02-26

申请号：US09519598

申请日：2000-03-06

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L2701

CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

公开(公告)号：US06319805B1

公开(公告)日：2001-11-20

申请号：US09499733

申请日：2000-02-08

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L213205

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/66507 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78621

摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

摘要翻译： 可以获得其中源极/漏极区域的寄生电阻可以比漏极区域的寄生电阻降低的半导体器件及其制造方法。 在半导体装置中，仅将钝化离子注入到半导体层的源极区域，以损坏半导体层的表面附近的晶体，从而促进了硅化反应。 因此，在源极区域中，可以形成更厚的硅化钛膜。

公开(公告)号：US06310377B1

公开(公告)日：2001-10-30

申请号：US09134896

申请日：1998-08-17

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC分类号： H01L2701

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76291 ,  H01L27/11807 ,  H01L27/1203

摘要： FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

摘要翻译： FS隔离场（10a，10b）。 LOCOS隔离场（11c，11d）。 FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i）按此顺序排列。 因此，可以提供主布局，其中将具有被提供固定电位的主体和具有不具有固定电位的主体的SOI晶体管混合。

公开(公告)号：US6144072A

公开(公告)日：2000-11-07

申请号：US231548

申请日：1999-01-15

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L21/76297 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654 ,  H01L21/26586

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US6127209A

公开(公告)日：2000-10-03

申请号：US295363

申请日：1999-04-21

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Hirotada Kuriyama ,  Shigeto Maegawa

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Hirotada Kuriyama ,  Shigeto Maegawa

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  H01L27/12 ,  H01L29/78 ,  H01L21/00 ,  H01L21/8232

CPC分类号： H01L27/092 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/7827

摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.

公开(公告)号：US6124619A

公开(公告)日：2000-09-26

申请号：US877202

申请日：1997-06-17

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L21/76 ,  H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L29/4232

摘要： In order to improve isolation between an FS (field shielding) electrode and a gate electrode (6), upper and lower major surfaces of a polysilicon layer (35) forming a principal part of an FS electrode (5) are covered with nitride films (SiN films) (34, 36) respectively. Therefore, it is possible to inhibit portions in the vicinity of edge portions of the polysilicon layer (35) from being oxidized by an oxidant following oxidation for forming a gate insulating film (14). Thus, the polysilicon layer (35) is inhibited from deformation following oxidation, whereby the distance between an FS electrode (5) and a gate electrode (6) is sufficiently ensured. Consequently, isolation between the FS electrode (5) and the gate electrode (6) is improved.

摘要翻译： 为了改善FS（场屏蔽）电极和栅电极（6）之间的隔离，形成FS电极（5）的主要部分的多晶硅层（35）的上主表面和下主表面被氮化物膜（ SiN膜）（34,36）。 因此，可以抑制多晶硅层（35）的边缘部分附近的部分被形成栅极绝缘膜（14）的氧化后的氧化剂氧化。 因此，抑制氧化后的多晶硅层（35）变形，从而充分确保了FS电极（5）与栅电极（6）之间的距离。 因此，提高了FS电极（5）与栅电极（6）之间的隔离。

公开(公告)号：US06025629A

公开(公告)日：2000-02-15

申请号：US746527

申请日：1996-11-12

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L29/66772 ,  H01L21/76224 ,  H01L21/76264 ,  H01L29/0638 ,  H01L29/78609 ,  H01L21/76281

摘要： A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

摘要翻译： 形成侧壁氧化物层和侧壁绝缘层以覆盖SOI层的边缘部分。 在SOI层的边缘部附近形成沟道阻挡区域。 在沟道阻挡区域上形成突出的绝缘层。 栅电极从SOI层上的区域延伸到突出的绝缘层和侧壁绝缘层。 以这种方式，可以抑制在SOI层的边缘部分处的寄生MOS晶体管的阈值电压Vth的降低。

公开(公告)号：US5990591A

公开(公告)日：1999-11-23

申请号：US027223

申请日：1998-02-20

申请人： Yasuo Yamaguchi ,  Masahiro Hasebe ,  Satoru Wakuta

发明人： Yasuo Yamaguchi ,  Masahiro Hasebe ,  Satoru Wakuta

IPC分类号： H02K1/22 ,  H02K1/27 ,  H02K15/03 ,  H02K21/16 ,  H02K21/12 ,  H02K1/00 ,  H02K19/00

CPC分类号： H02K1/276 ,  H02K1/2766 ,  H02K7/006

摘要： A permanent magnet type synchronous motor includes an iron core rotor having a plurality of holes which are circumferentially spaced, permanent magnets mounted in the holes, an iron core stator and coils arranged in the stator iron core. The permanent magnets are defined by a flat surface extending tangentially of the rotor, tapered surfaces formed at both ends of the flat surface and extending obliquely outward in a direction approaching each other, and an arcuate surface joining the two tapered surfaces. Each permanent magnet is supported by tapered surfaces formed at opposing ends of the holes and extending obliquely and radially outward in a direction approaching each other. When the rotor is rotated, the centrifugal force is received at the tapered surfaces of the holes, rather than at their arcuate portion.

摘要翻译： 永磁式同步电动机包括铁心转子，铁芯转子具有周向间隔开的多个孔，安装在孔中的永磁体，铁芯定子和布置在定子铁心中的线圈。 永久磁铁由转子切向平坦的平面限定，在平坦表面的两端形成锥形表面，并且在彼此靠近的方向上倾斜向外延伸，并且连接两个锥形表面的弓形表面。 每个永磁体由形成在孔的相对端处的锥形表面支撑，并且在彼此接近的方向上倾斜并径向向外延伸。 当转子旋转时，离心力被接收在孔的锥形表面处，而不是在其弓形部分处。

公开(公告)号：US5926703A

公开(公告)日：1999-07-20

申请号：US785277

申请日：1997-01-21

申请人： Yasuo Yamaguchi ,  Hans-Oliver Joachim ,  Yasuo Inoue

发明人： Yasuo Yamaguchi ,  Hans-Oliver Joachim ,  Yasuo Inoue

IPC分类号： H01L29/40 ,  H01L21/336 ,  H01L27/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L29/66757 ,  H01L27/1203 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78621

摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.

摘要翻译： 本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。 导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'） ）。 在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。 在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。 仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。