公开(公告)号：US09980219B2

公开(公告)日：2018-05-22

申请号：US15808592

申请日：2017-11-09

Applicant: STMICROELECTRONICS, INC.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W52/02 ,  H04W8/22 ,  H04W88/02 ,  H04W88/08 ,  H04W84/12

CPC classification number: H04W52/0209 ,  H04W8/22 ,  H04W52/0206 ,  H04W52/0216 ,  H04W52/0222 ,  H04W52/0229 ,  H04W84/12 ,  H04W88/02 ,  H04W88/08 ,  Y02D70/00 ,  Y02D70/142

Abstract: A IEEE 802.11 Wireless Local Area Network (WLAN) system of an access point (AP) and one or more stations (STAs) reduces power consumption and increases battery life of power efficient low power STAs by decreasing the amount of time that a power efficient low power STA remains in an awake state. After indicating power efficient low power operation during association with an AP supporting such operation, the power efficient low power STA may enter the doze state from the time that the power efficient low power STA sends a PS-Poll until the power efficient low power STA receives the buffered DATA frame from the AP. While implementing the power efficient PS-Poll method, the AP can send the buffered DATA frame to the STA SIFS after the AP sends an ACK to the received PS-Poll from the STA.

公开(公告)号：US09972558B1

公开(公告)日：2018-05-15

申请号：US15479068

申请日：2017-04-04

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Tito Mangaoang

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/46 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/92125

Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

公开(公告)号：US09968700B2

公开(公告)日：2018-05-15

申请号：US14975200

申请日：2015-12-18

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Simon Dodd ,  Joseph Edward Scheffelin ,  Dave S. Hunt ,  Timothy James Hoekstra ,  Faiz Sherman ,  Stephan Gary Bush

IPC: A61L9/03 ,  B05B17/06 ,  A61L2/00 ,  A61L9/00

CPC classification number: A61L9/03 ,  A61L2/00 ,  A61L9/00 ,  B05B17/0684

Abstract: One or more embodiments are directed to a microfluidic delivery system that dispenses a fluid. The microfluidic delivery system may be provided in a variety of orientations. In one embodiment, the microfluidic delivery system is vertical so that fluid being expelled opposes gravity. In another embodiment, the microfluidic delivery system is orientated sideways so that fluid being expelled has a horizontal component. In yet another embodiment, the microfluidic delivery system faces downward.

公开(公告)号：US09953933B1

公开(公告)日：2018-04-24

申请号：US15474904

申请日：2017-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Rennier Rodriguez ,  Ela Mia Cadag

IPC: H01L23/552 ,  H01L23/00 ,  B32B7/12 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/552 ,  B32B7/12 ,  B32B2457/14 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48229 ,  H01L2224/48992 ,  H01L2924/15311 ,  H01L2924/3025

Abstract: A semiconductor package includes a substrate, a die, an insulating die attach film, a dummy die, a conductive layer, and an electrically conductive molding compound or encapsulant. The first surface of the substrate includes a plurality of internal leads, and the second surface of the substrate includes a plurality of external electrically conductive pads and an electrically conductive ground terminal. A non-conductive flow over wire die attach film is placed to surround and encase the die. The dummy die overlies the die and a conductive layer overlies the dummy die. The electrically conductive molding compound is formed to encase the various components of the semiconductor device. The electrically conductive molding compound is electrically coupled to the electrically conductive ground terminal and the conductive layer forming an EMI shield for the die in the package.

公开(公告)号：US09947772B2

公开(公告)日：2018-04-17

申请号：US14231466

申请日：2014-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7845 ,  H01L29/785

Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

公开(公告)号：US09939481B2

公开(公告)日：2018-04-10

申请号：US15603181

申请日：2017-05-23

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.r.l.

Inventor： Oleg Logvinov ,  Roberto Cappelletti ,  Mauro Conti

IPC: H01H31/12 ,  G01R31/02 ,  H04B3/54

CPC classification number: G01R31/024 ,  H04B3/54 ,  H04B2203/5458 ,  H04B2203/5495

Abstract: Embodiments of the present disclosure include a method of operating an arc fault detection system, an arc fault detection system, and a system. An embodiment is a method of operating an arc fault detection system coupled to a power line, the method including determining one or more arc fault detection windows in power line signals on the power line, the power line signals comprising a communication signal and an alternating current (AC) power signal. The method further includes receiving the power line signals from the power line during the one or more arc fault detection windows, and performing arc fault detection processing on the received power line signals.

公开(公告)号：US20180096256A1

公开(公告)日：2018-04-05

申请号：US15833457

申请日：2017-12-06

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics, Inc.

Inventor： Mahesh Chowdhary ,  Arun Kumar ,  Ghanapriya Singh ,  Kashif R. J. Meer ,  Indra Narayan Kar ,  Rajendar Bahl

IPC: G06N7/00 ,  G06F17/30

CPC classification number: G06N7/005 ,  G06F16/2455 ,  H04M1/72569 ,  H04W4/02 ,  H04W4/38

Abstract: An electronic device described herein includes a sensing unit having at least one sensor to acquire sensing data. An associated computing device extracts sensor specific features from the sensing data, and generates a motion activity vector, a voice activity vector, and a spatial environment vector as a function of the sensor specific features. The motion activity vector, voice activity vector, and spatial environment vector are processed to determine a base level context of the electronic device relative to its surroundings, with the base level context having aspects each based on the motion activity vector, voice activity vector, and spatial environment vector. Meta level context of the electronic device relative to its surroundings is determined as a function of the base level context, with the meta level context being at least one inference made from at least two aspects of the plurality of aspects of the base level context.

公开(公告)号：US09935179B2

公开(公告)日：2018-04-03

申请号：US15472556

申请日：2017-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

公开(公告)号：US09922993B2

公开(公告)日：2018-03-20

申请号：US15292465

申请日：2016-10-13

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L29/417 ,  H01L21/84 ,  H01L29/66 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/1211 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/845 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

公开(公告)号：US09905478B2

公开(公告)日：2018-02-27

申请号：US15469851

申请日：2017-03-27

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.