公开(公告)号：US20150041625A1

公开(公告)日：2015-02-12

申请号：US14451482

申请日：2014-08-05

Applicant: STMicroelectronics (Research & Development) Limited

Inventor： Neale Dutton ,  Robert K. Henderson ,  Salvatore Gnecchi

IPC: G04F10/00 ,  G01T1/24

CPC classification number: G04F10/005 ,  G01S7/4865 ,  G01S17/10 ,  G01T1/248 ,  G01T1/2985

Abstract: A time to digital converter includes a sample module operable to sample an input signal at multiple different instances of time. A transition detection module, formed of comparison elements, processes the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time. An output module generates detected transitions in the input signal on multiple parallel outputs.

Abstract translation: 时间到数字转换器包括可操作以在多个不同的时间点对输入信号进行采样的采样模块。 由比较元件形成的转换检测模块在连续的时间实例处理采样的输入信号，以便检测输入信号在时间上的转变。 输出模块在多个并行输出上产生输入信号中检测到的转换。

公开(公告)号：US08941524B2

公开(公告)日：2015-01-27

申请号：US13874531

申请日：2013-05-01

Applicant: Semiconductor Technology Academic Research Center

Inventor： Hiroshi Kawaguchi ,  Masahiko Yoshimoto ,  Toshihiro Konishi ,  Shintaro Izumi ,  Keisuke Okuno

IPC: H03M1/50 ,  G04F10/00

CPC classification number: H03M1/50 ,  G04F10/005

Abstract: A TD converter is provided for digitally converting a delay time value into a digital value. In the TD converter, an oscillator circuit part inputs time domain data. A first-state counter circuit part measures a number of waves of an output oscillation waveform from the oscillator circuit part when time domain data is in a first state, and a second-state counter circuit part measures a number of waves of the output oscillation waveform from the oscillator circuit part when the time domain data is in a second state. An output signal generator part generates an output signal based on output count values of the first-state counter circuit part and the second-state counter circuit part, and a frequency control circuit controls the oscillator circuit part to always oscillate and to control an oscillation frequency of the oscillator circuit part.

Abstract translation: 提供了一种TD转换器，用于将延迟时间值数字转换为数字值。 在TD转换器中，振荡器电路部分输入时域数据。 当时域数据处于第一状态时，第一状态计数器电路部分测量来自振荡器电路部分的输出振荡波形的波数，并且第二状态计数器电路部分测量输出振荡波形的波数 当时域数据处于第二状态时，来自振荡器电路部分。 输出信号发生器部分基于第一状态计数器电路部分和第二状态计数器电路部分的输出计数值产生输出信号，并且频率控制电路控制振荡器电路部分总是振荡并控制振荡频率 的振荡器电路部分。

公开(公告)号：US08896477B2

公开(公告)日：2014-11-25

申请号：US14265148

申请日：2014-04-29

Applicant: Panasonic Corporation

Inventor： Shiro Dosho ,  Masao Takayama

IPC: H03M1/50 ,  G04F10/00 ,  H03M1/18 ,  H03M1/12 ,  H03L7/087 ,  H03M1/00 ,  H03L7/081 ,  H03L7/18

CPC classification number: G04F10/005 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/18 ,  H03M1/00 ,  H03M1/12 ,  H03M1/18 ,  H03M2201/4233

Abstract: An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter.

Abstract translation: 边沿检测器包括接收环形振荡器的相位信号的触发器，在输入信号的边缘定时取消触发器的复位状态的复位器，以及对触发器的输出信号执行逻辑运算的逻辑运算器， 翻牌 相位状态检测器基于触发器的输出信号来检测在输入信号的边缘定时处发生的环形振荡器的相位状态。 时间 - 数字转换器将输入信号和逻辑运算器的输出信号之间的边沿间隔转换为数字值。 在输入信号的边缘定时处，锁存器锁存计数环形振荡器的输出信号的周期数的计数器的值。 操作者根据锁存器，相位状态检测器和时间 - 数字转换器的输出信号计算接收信号的数字值。

公开(公告)号：US20140330117A1

公开(公告)日：2014-11-06

申请号：US14336995

申请日：2014-07-21

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Medical Systems Corporation

Inventor： Gregory J. Mann

IPC: G04F10/00 ,  A61B6/00 ,  G01T1/29 ,  H03L5/00 ,  H03M1/10

CPC classification number: G04F10/005 ,  A61B6/4417 ,  G01T1/2985 ,  H03L5/00 ,  H03M1/1009

Abstract: An apparatus for inserting delay according to an embodiment includes a signal generating circuit, a plurality of carry elements, and a delay chain circuit. The delay chain circuit includes one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs. Each of the plurality of enable inputs is provided in a respective one of the delay modules. The delay chain circuit is configured to generate an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay, and is configured to provide the selected amount of delay to the signal generating circuit, which is configured to incorporate the delay into the start signal.

Abstract translation: 根据实施例的用于插入延迟的装置包括信号发生电路，多个进位元件和延迟链电路。 延迟链电路包括从多个进位元件中选择的一个或多个延迟模块，连接在至少一个延迟模块和信号发生电路之间的至少一个反馈线以及多个使能输入。 多个使能输入中的每一个被提供在相应的一个延迟模块中。 延迟链电路被配置为基于在使能输入处接收的延迟选择信号产生一定量的延迟，并且选择延迟量，并且被配置为向信号发生电路提供所选择的延迟量， 被配置为将延迟并入起始信号。

公开(公告)号：US08855181B2

公开(公告)日：2014-10-07

申请号：US13760198

申请日：2013-02-06

Applicant: Infineon Technologies AG

Inventor： Jens Barrenscheen

IPC: H04L12/26 ,  H04L7/00 ,  H03M1/12 ,  H02P27/08

CPC classification number: H03M3/462 ,  G04F10/005 ,  H02P27/08 ,  H03M1/12 ,  H03M3/37 ,  H03M3/458 ,  H04L7/0033

Abstract: A method and a system for compensating a delay mismatch between a first measurement channel and a second measurement channel is disclosed. A method for compensating a delay mismatch between a first measurement channel and a second measurement channel includes providing a reference point for starting the first and second measurement channel, and starting the first measurement channel after expiration of a first delay period which begins at the reference point. The method further includes starting the second measurement channel after expiry of a second delay period which begins at the reference point, wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

Abstract translation: 公开了一种用于补偿第一测量通道和第二测量通道之间的延迟失配的方法和系统。 用于补偿第一测量信道和第二测量信道之间的延迟失配的方法包括提供用于启动第一和第二测量信道的参考点，以及在从参考点开始的第一延迟周期到期之后启动第一测量信道 。 该方法还包括在从参考点开始的第二延迟周期到期之后启动第二测量信道，其中第一延迟周期的长度与第二延迟周期的长度之间的差基本上等于 第一测量通道和第二测量通道。

公开(公告)号：US08847812B2

公开(公告)日：2014-09-30

申请号：US13589550

申请日：2012-08-20

Applicant: Shiro Dosho ,  Takuji Miki

Inventor： Shiro Dosho ,  Takuji Miki

IPC: H03M1/50 ,  G04F10/00 ,  H03K5/151

CPC classification number: G04F10/005 ,  H03K5/1515 ,  H03M1/50

Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from −(2n-1−1) to +(2n-1−1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.

Abstract translation: 在时间数字转换阶段，时间数字转换电路输出表示从 - （2n-1-1）到+（2n-1-1）的整数值的n位数字信号， 基于输入到其的第一和第二信号之间的相位差; 时差放大器电路将第一和第二信号2n-1次之间的相位差放大倍数，并输出两个放大相位差的信号; 延迟调整电路将与数字信号相关的相位差与从时差放大器电路输出的两个信号相加，并输出另外两个信号; 输出检测电路检测出延迟调整电路输出了另外两个信号，并输出检测信号; 并且存储电路与检测信号同步地锁存数字信号。 时间 - 数字转换级的多级耦合形成流水线时间 - 数字转换器。

公开(公告)号：US08836568B2

公开(公告)日：2014-09-16

申请号：US13755312

申请日：2013-01-31

Applicant: Dariusz Koscielnik ,  Marek Miskowicz

Inventor： Dariusz Koscielnik ,  Marek Miskowicz

IPC: H03M1/12 ,  G04F10/10

CPC classification number: H03M1/12 ,  G04F10/005 ,  G04F10/105

Abstract: Method and apparatus for accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (Cn) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next gate signal (Gx+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent gate signal (Gx+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again.

Abstract translation: 用于累积传送到采样电容器（Cn）中的电荷输入（InQ）的电荷的方法和装置，以及通过改变来自相关控制输出的信号的状态来实现再分配阵列（A）中的电荷再分配的过程，以及 通过控制模块（CM）将相关值分配给数字字中的位。 方法的特征在于，在检测到下一个栅极信号（Gx + 1）的开始后，电荷累积在附加采样电容器（CnA）中，然后实现电荷再分配的处理，并将相关值分配给位 的数字词。 当检测到后续门信号（Gx + 2）的开始时，下一个周期开始，电荷再次累积在采样电容器（Cn）中。

公开(公告)号：US08830110B1

公开(公告)日：2014-09-09

申请号：US13792558

申请日：2013-03-11

Applicant: Nvidia Corporation

Inventor： Dong-Myung Choi ,  Madhusudhan Sarda ,  Anu Subbaraman ,  Kwanjee Ng

IPC: H03M1/50 ,  H03M1/64 ,  G04F10/00 ,  H03M1/60

CPC classification number: H03M1/50 ,  G04F10/005 ,  H03M1/60

Abstract: A window-enabled TDC and method of detecting phase of a reference signal. One embodiment of the window-enabled TDC includes: (1) a window generator configured to receive a reference signal and a clock signal, and (2) a TDC circuit coupled to the window generator and configured to be enabled based on the reference signal and disabled based on the clock signal.

Abstract translation: 一种支持窗口的TDC和检测参考信号相位的方法。 启用窗口的TDC的一个实施例包括：（1）窗口生成器，其被配置为接收参考信号和时钟信号，以及（2）TDC电路，其耦合到窗口发生器并且被配置为基于参考信号被使能， 基于时钟信号禁用。

公开(公告)号：US08822935B2

公开(公告)日：2014-09-02

申请号：US13319107

申请日：2010-04-15

Applicant: Thomas Frach ,  Gordian Prescher

Inventor： Thomas Frach ,  Gordian Prescher

IPC: G01T1/17 ,  H03K5/22 ,  G04F10/00 ,  A61B6/03 ,  G01T1/29

CPC classification number: G01T1/2985 ,  A61B6/037 ,  G04F10/005 ,  H03K5/22 ,  H03M1/0827 ,  H03M1/0836

Abstract: A radiation detector module (10) for use in a time-of-flight positron emission tomography (TOF-PET) scanner (8) generates a trigger signal indicative of a detected radiation event. A timing circuit (22) including a first time-to-digital converter (TDC) (30) and a second TDC (31) is configured to output a corrected timestamp for the detected radiation event based on a first timestamp determined by the first TDC (30) and a second timestamp determined by the second TDC (31). The first TDC is synchronized to a first reference clock signal (40, 53) and the second TDC is synchronized to a second reference clock signal (42, 54), the first and second reference clock signals being asynchronous.

Abstract translation: 用于飞行时间正电子发射断层摄影（TOF-PET）扫描仪（8）的放射线检测器模块（10）产生指示检测到的辐射事件的触发信号。 包括第一时间数字转换器（TDC）（30）和第二TDC（31）的定时电路（22）被配置为基于由第一TDC（31）确定的第一时间戳输出用于检测到的辐射事件的校正时间戳 （30）和由所述第二TDC（31）确定的第二时间戳。 第一TDC与第一参考时钟信号（40,53）同步，并且第二TDC与第二参考时钟信号（42,54）同步，第一和第二参考时钟信号是异步的。

公开(公告)号：US20140203798A1

公开(公告)日：2014-07-24

申请号：US13997604

申请日：2012-03-30

Applicant: Frank O'Mahony ,  Bryan K. Casper ,  Mozhgan Mansuri

Inventor： Frank O'Mahony ,  Bryan K. Casper ,  Mozhgan Mansuri

IPC: G01R31/317

CPC classification number: G01R31/31725 ,  G01R25/08 ,  G01R31/31726 ,  G04F10/005 ,  H03K2005/00052

Abstract: An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.

Abstract translation: 在集成电路（IC）芯片上构造的全数字延迟测量电路（DMC）表征了也在IC芯片上构造的诸如全相位旋转内插器的时钟电路。 片上全数字DMC产生与两个时钟之间的相对延迟成比例的数字输出值，归一化为两个时钟的时钟周期。