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公开(公告)号：US20180068734A1
公开(公告)日：2018-03-08
申请号：US15286829
申请日：2016-10-06
申请人： Shannon Systems Ltd.
发明人： Zhen ZHOU
CPC分类号： G11C16/26 , G06F9/4401 , G06F11/1048 , G06F11/1068 , G06F11/1417 , G11C16/20 , G11C29/52 , G11C2029/0411
摘要： The invention introduces a method for read retries, performed by a processing unit, including at least the following steps: in boot time, generating and storing microcodes of a retry-read operation in an instruction buffer; and after a successful boot, receiving a retry-read command from a host device through a first access interface; and starting a state machine to execute the microcodes of the retry-read operation of the instruction buffer.
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公开(公告)号：US20180067798A1
公开(公告)日：2018-03-08
申请号：US15255368
申请日：2016-09-02
IPC分类号： G06F11/10 , G06F12/1009 , G06F3/06
CPC分类号： G06F11/1048 , G06F3/0619 , G06F3/064 , G06F3/0673
摘要： Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.
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公开(公告)号：US20180067719A1
公开(公告)日：2018-03-08
申请号：US15255543
申请日：2016-09-02
CPC分类号： G06F7/14 , G06F3/0619 , G06F11/00 , G06F11/0766 , G06F11/0772 , G06F11/1016 , G06F11/1048 , G06F11/1064 , G06F11/1076 , G06F16/2282
摘要： Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.
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公开(公告)号：US20180061510A1
公开(公告)日：2018-03-01
申请号：US15447310
申请日：2017-03-02
申请人： SK hynix Inc.
发明人： Ju Hyeon HAN , Jong Won PARK , Chan Woo YANG
CPC分类号： G11C29/50004 , G06F11/1044 , G06F11/1048 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2029/5004
摘要： A data storage device includes a nonvolatile memory device; and a control unit suitable for controlling a program operation for memory cells of a page of the nonvolatile memory device, and processing a program fail in the case where the program operation fails, wherein the control unit adjusts a read voltage for discriminating an erase state and a program state having a threshold voltage most adjacent to the erase state, reads out data by applying the adjusted read voltage to the memory cells of the page, and performs an error handling operation to data stored in the memory cells of the page according to a result of comparing a reference value and a number of flipped bits of the data read out by applying the varied read voltage.
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公开(公告)号：US20180061498A1
公开(公告)日：2018-03-01
申请号：US15556680
申请日：2015-06-19
申请人： Hitachi, Ltd.
发明人： Yohei HAZAMA , Junji OGAWA , Kenta NINOSE
CPC分类号： G11C16/26 , G06F3/067 , G06F3/0688 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G06F12/16 , G11C11/5642 , G11C16/349 , G11C2211/5648
摘要： A flash memory controller is configured to hold a read pattern defining an order of selection of read options specifying a parameter value for a read from the flash memory chip. The flash memory controller is configured to execute error correction on data read from the flash memory chip in accordance with the read command. The flash memory controller is configured to designate a next read option specified in the read pattern to read the data from the flash memory chip in a case where all errors in the read data are not corrected by the error correction.
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公开(公告)号：US20180060194A1
公开(公告)日：2018-03-01
申请号：US15596540
申请日：2017-05-16
发明人： Ye-Sin RYU , Jong-Wook PARK , Youn-Hyung KANG
CPC分类号： G06F11/1666 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1048 , G06F11/108 , G06F2201/805 , G11C29/52 , G11C2029/0411
摘要： A method of operating a semiconductor memory device including a memory cell array and an error correction code (ECC) engine, wherein the memory cell array includes a plurality of memory cells and the ECC engine is configured to perform an error correction operation on data of the memory cell array, may include storing, in a nonvolatile storage, a mapping information indicating physical addresses of normal cells to swap with a portion of fail cells when a first unit of memory cells includes a number of the fail cells exceeding an error correction capability of the ECC engine. The first unit of memory cells of the memory cells may be accessed based on a logical address. The method may include performing a memory operation on the memory cell array selectively based on the mapping information.
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公开(公告)号：US09904592B2
公开(公告)日：2018-02-27
申请号：US14775848
申请日：2014-02-26
申请人： Intel Corporation
IPC分类号： G11C29/00 , G06F11/10 , G06F12/0866 , G06F12/084
CPC分类号： G06F11/1064 , G06F11/1048 , G06F12/084 , G06F12/0866 , G06F2212/1032 , G06F2212/313
摘要： Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.
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公开(公告)号：US09899094B2
公开(公告)日：2018-02-20
申请号：US15189725
申请日：2016-06-22
申请人： SK hynix Inc.
发明人： Ji Man Hong
CPC分类号： G11C16/3418 , G06F11/1048 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3422 , G11C16/3427 , G11C16/3431
摘要： A nonvolatile memory device includes a memory block including a plurality of memory cells which are coupled to a plurality of word lines; and a control unit configured to perform a read operation in response to a read command for target memory cells which are coupled to a target word line, wherein the control unit performs the read operation by applying a read bias voltage to the target word line, applying a first pass bias to a monitoring word line, applying a second pass bias to one or more adjacent word lines adjacent to the target word line, and applying a third pass bias to remaining word lines.
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公开(公告)号：US20180046538A1
公开(公告)日：2018-02-15
申请号：US15473237
申请日：2017-03-29
申请人： SK Hynix Inc.
发明人： Fan Zhang , Chenrong Xiong , Yu Cai , Aman Bhatia , HyungSeok Kim , June Lee
CPC分类号： G06F11/1048 , G06F3/0604 , G06F3/0631 , G06F3/0644 , G06F3/0683 , G06F11/102 , G06F11/108
摘要： A memory device including a memory having a plurality of memory cells for storing data. The memory device includes a controller communicatively coupled to the memory and configured to organize the data as a plurality of stripes. Each individual stripe of the plurality of stripes includes a plurality of data groups, each of the plurality of data groups stored in the memory using a subset of the plurality of memory cells. Stripe lengths (number of data groups) for individual stripes are determined by the controller based on detecting a condition associated with one or more data groups of the plurality of data groups. At least one data group of the plurality of data groups for each of the individual stripes includes parity data for correcting bit errors associated with the subset of the plurality of memory cells for the individual stripe.
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公开(公告)号：US09891988B2
公开(公告)日：2018-02-13
申请号：US15467348
申请日：2017-03-23
发明人： Tobias Blaettler , Thomas Mittelholzer , Nikolaos Papandreou , Thomas Parnell , Charalampos Pozidis , Milos Stanisavljevic
CPC分类号： G06F11/1048 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C16/10 , G11C2211/5648
摘要： A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.
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