公开(公告)号：US20050030313A1

公开(公告)日：2005-02-10

申请号：US10931376

申请日：2004-08-31

申请人： William Radke ,  James Peterson

发明人： William Radke ,  James Peterson

IPC分类号： G06F13/16 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393

CPC分类号： G09G5/363 ,  G06F13/1657 ,  G09G5/393 ,  G09G2360/121

摘要： A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

摘要翻译： 一种用于图形处理系统的分布式存储器控制器存储器系统，其具有可寻址存储区域，每个存储器区域耦合到相应的存储器控​​制器。 存储器控制器还通过存储器控制器总线彼此耦合，在存储器控制器总线上，存储器访问请求和数据可以从一个存储器控制器传递到其他存储器控制器。 对一个可寻址存储器区域中的存储器位置的存储器访问请求，但是由耦合到另一可寻址存储区域的存储器控​​制器接收的存储器访问请求从存储器控制器总线从接收存储器控制器传递到存储器控制器，该存储器控制器耦合到可寻址存储器区域 为了服务存储器访问请求，所请求的位置所在的位置。 耦合到相应的可寻址存储器区域的附加存储器控制器可以被包括在存储器系统中。 存储器控制器耦合到存储器控制器总线，以便接收并传递来自其它存储器控制器的存储器访问请求。

公开(公告)号：US20040019756A1

公开(公告)日：2004-01-29

申请号：US10302420

申请日：2002-11-22

发明人： Richard E. Perego ,  Donald C. Stark ,  Frederick A. Ware

IPC分类号： G06F013/00

CPC分类号： G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

摘要翻译： 描述了存储器系统，其中存储器核心组织随设备宽度而变化。 所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。 增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

公开(公告)号：US20030046477A1

公开(公告)日：2003-03-06

申请号：US09942389

申请日：2001-08-29

发明人： Joseph Jeddeloh

IPC分类号： G06F013/00

CPC分类号： G06F13/1657 ,  G06F13/1647

摘要： In a computer or microprocessor-based system having a plurality of resources making memory requests of a plurality of banks of memory, a switch-based interconnect system allows multiple simultaneous connections between resources and memory banks, maximizing memory throughput and bandwidth concurrency. The invention is particularly useful in devices having embedded banks of memory, where there are no external constraints requiring use of a bus architecture, but can be used with discrete devices as well.

摘要翻译： 在具有多个存储器请求的多个资源的基于计算机或微处理器的系统中，基于交换机的互连系统允许资源和存储体之间的多个同时连接，从而最大化存储器吞吐量和带宽并发性。 本发明在具有嵌入式存储器组的设备中特别有用，其中不存在需要使用总线架构的外部约束，但也可以与分立器件一起使用。

公开(公告)号：US06516343B1

公开(公告)日：2003-02-04

申请号：US09557380

申请日：2000-04-24

申请人： Fong Pong ,  Tung Nguyen

发明人： Fong Pong ,  Tung Nguyen

IPC分类号： G06F1300

CPC分类号： G06F13/1657 ,  G06F12/0808

摘要： A computer system and method for enhancing memory-to-memory copy operations includes transmitting from the processor to the source system control unit a plurality of memory-to-memory copy transactions where each transaction includes a source address and a destination address. A lookup operation is performed on the destination address to determine the destination system control unit that controls access to the destination memory which contains the destination address. A number of data blocks located at the source address in the source memory are retrieved and transmitted to the destination address. The number of data blocks are stored at the destination address in the destination memory.

摘要翻译： 用于增强存储器到存储器复制操作的计算机系统和方法包括从处理器向源系统控制单元发送多个存储器到存储器复制事务，其中每个事务包括源地址和目的地地址。 对目的地址执行查找操作，以确定控制对包含目的地地址的目的地存储器的访问的目的地系统控制单元。 位于源存储器中的源地址处的多个数据块被检索并发送到目的地址。 数据块的数量存储在目的地存储器中的目的地址中。

公开(公告)号：US06360306B1

公开(公告)日：2002-03-19

申请号：US09231236

申请日：1999-01-15

申请人： James R. Bergsten

发明人： James R. Bergsten

IPC分类号： G06F1200

CPC分类号： G06F13/1657 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0689 ,  G06F11/201 ,  G06F11/2058 ,  G06F11/2069 ,  G06F11/2071 ,  G06F11/2094 ,  G06F11/2097 ,  Y10S707/99953 ,  Y10S707/99954 ,  Y10S707/99955

摘要： A network comprises at least one host processing system, a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be coupled to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing. During a data access, the storage controller connected to the accessing host maps a virtual address provided by the host to a real physical location in any of the storage arrays, such that the actual location of the data is transparent to the host. The storage controllers provide automatic back-up and error correction as well as write protection of back-up copies.

摘要翻译： 网络包括至少一个主机处理系统，多个存储控制器，每个存储控制器都耦合到多个存储阵列中的一个，每个存储阵列包括至少一个大容量存储设备。 每个存储控制器可以耦合到至少一个主机处理系统和至少一个其他存储控制器，以控制主处理系统对大容量存储设备的访问。 多个数据副本被保存在地理上彼此远的存储阵列中，以便任何主机可以访问任何副本。 每个存储控制器包括与模拟大容量存储设备的主机的接口以及模拟主机的本地存储阵列的接口。 与主机和本地存储阵列的接口与本地存储阵列中主机或设备的类型无关。 两个或多个主机可能彼此不相似，并且两个或更多个存储阵列可以包括不同的大容量存储设备。 主机使用虚拟寻址访问存储的数据。 在数据访问期间，连接到访问主机的存储控制器将由主机提供的虚拟地址映射到任何存储阵列中的真实物理位置，使得数据的实际位置对主机是透明的。 存储控制器提供自动备份和纠错以及备份副本的写保护。

公开(公告)号：US06311286B1

公开(公告)日：2001-10-30

申请号：US08258752

申请日：1994-06-10

申请人： James F. Bertone ,  Bruno DiPlacido, Jr. ,  Thomas F Joyce ,  Martin Massucci ,  Lance J. McNally ,  Thomas L. Murray, Jr. ,  Chester M. Nibby, Jr. ,  Michelle A. Pence ,  Marc Sanfacon ,  Jian-Kuo Shen ,  Jeffrey S. Somers ,  G. Lewis Steiner

发明人： James F. Bertone ,  Bruno DiPlacido, Jr. ,  Thomas F Joyce ,  Martin Massucci ,  Lance J. McNally ,  Thomas L. Murray, Jr. ,  Chester M. Nibby, Jr. ,  Michelle A. Pence ,  Marc Sanfacon ,  Jian-Kuo Shen ,  Jeffrey S. Somers ,  G. Lewis Steiner

IPC分类号： G06F926

CPC分类号： G06F13/1657 ,  G06F12/0831 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/368

摘要： The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.

摘要翻译： 本发明涉及一种与具有不同时序特征的存储器一起使用的存储器控​​制器。 具体地，确定各种存储器件的定时特性并用于产生与每个特定存储器件相称的定时信号。

公开(公告)号：US06178466B1

公开(公告)日：2001-01-23

申请号：US09096822

申请日：1998-06-12

申请人： Roger Lee Gilbertson ,  Mitchell Anthony Bauman

发明人： Roger Lee Gilbertson ,  Mitchell Anthony Bauman

IPC分类号： G06F1314

CPC分类号： G06F13/1657

摘要： A control system and interface is provided for controlling the transmission of address and data signals via independently operative bi-directional address and data interfaces, respectively, within a data processing system. The system allows address signals to be transferred via the address interface either before, or after, associated data signals are transferred. The address interface operates at a rate which is independent of the rate achieved on the data interface. Address signals transferred on the address interface are stored in one of a plurality of address storage devices depending on request type. A routing circuit associates later-provided data signals with the address storage device storing the associated address signals, and a correlation circuit allows the address storage device to record the data transfer with the associated address signals. According to one embodiment, the correlation is performed using a pointer indicative of a storage location temporarily storing the data signals. If the data signals are transferred prior to the associated address signals, the data signals are temporarily stored until the associated address signals are transferred, sorted, and associated with a selected one of the address storage devices. Following correlation of address and data signals, the associated request is eligible for processing based on the availability of the requested resource.

摘要翻译： 提供控制系统和接口，用于分别在数据处理系统内经由独立操作的双向地址和数据接口来控制地址和数据信号的传输。 该系统允许在相关数据信号被传送之前或之后通过地址接口传送地址信号。 地址接口以与数据接口上实现的速率无关的速率工作。 在地址接口上传送的地址信号根据请求类型存储在多个地址存储设备之一中。 路由电路将稍后提供的数据信号与存储相关联的地址信号的地址存储设备相关联，并且相关电路允许地址存储设备用相关联的地址信号记录数据传输。 根据一个实施例，使用指示临时存储数据信号的存储位置的指针来执行相关。 如果在相关联的地址信号之前传送数据信号，则暂时存储数据信号，直到相关联的地址信号被传送，分类并与所选择的一个地址存储设备相关联。 根据地址和数据信号的相关性，相关联的请求可以根据请求的资源的可用性进行处理。

公开(公告)号：US6021086A

公开(公告)日：2000-02-01

申请号：US133287

申请日：1998-08-12

申请人： Alexander Joffe

发明人： Alexander Joffe

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  H04L12/44 ,  H04L12/56 ,  G11C11/401

CPC分类号： H04L12/5601 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/1663 ,  H04L49/103 ,  H04L49/108 ,  H04L49/1553 ,  H04L49/1576 ,  H04L49/3081 ,  H04L49/606 ,  H04L2012/5678 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L49/101 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/351 ,  H04L49/40

摘要： A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible a master data path for the transfer data to or from the bus interface unit and which includes an externally accessible slave data path for the transfer of data to or from the buffer and which includes a direct data path for the transfer data between the bus interface unit and the buffet.

摘要翻译： 一种存储器接口单元，包括总线接口单元，可以存储在数字存储器中或从数字存储器传送数据的多个数据突发子集的缓冲器，以及包括用于向或从总线接口传输数据的外部可访问的主数据路径的开关 并且其包括用于向缓冲器传送数据或从缓冲器传送数据的外部可访问的从属数据路径，并且其包括用于总线接口单元和自助餐之间的传送数据的直接数据路径。

公开(公告)号：US5970510A

公开(公告)日：1999-10-19

申请号：US629839

申请日：1996-04-10

申请人： Richard A. Sher ,  Jerry Rogers ,  Mark J. Wentka

发明人： Richard A. Sher ,  Jerry Rogers ,  Mark J. Wentka

IPC分类号： G06F9/345 ,  G06F13/16 ,  G06F9/45

CPC分类号： G06F9/3455 ,  G06F13/1657 ,  G06F13/1663 ,  G06F9/345

摘要： A distributed memory addressing system has a plurality of separate processing elements. Each processing element has at least one CPU. A shared memory is utilized to store data to be used by the separate processing elements, as required. A high bandwidth interface interconnects processing elements and the shared memory. The high bandwidth interface is configured so as to provide non-blocking access to the shared memory for each of the processing elements.

摘要翻译： 分布式存储器寻址系统具有多个单独的处理元件。 每个处理元件具有至少一个CPU。 根据需要，共享存储器被用于存储要由单独的处理元件使用的数据。 高带宽接口将处理元件和共享存储器互连。 配置高带宽接口以便为每个处理元件提供对共享存储器的非阻塞访问。

公开(公告)号：US5812782A

公开(公告)日：1998-09-22

申请号：US850888

申请日：1997-05-02

申请人： Gary Edward Jackson

发明人： Gary Edward Jackson

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F13/14 ,  G06F15/16

CPC分类号： G06F3/0601 ,  G06F13/1657 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0635 ,  G06F3/0689 ,  G06F2003/0692

摘要： A pair of data processing systems, each having a host CP and a controller, both systems to be operatively associated with a number of like memory units, each unit coupled to both controllers, wherein either host CP/controller can appropriate any "selected" memory unit by simply propagating "path-control-data" to memory in both controllers and in the selected memory unit.

摘要翻译： 一对数据处理系统，每个具有主机CP和控制器，两个系统可操作地与多个类似的存储器单元相关联，每个单元耦合到两个控制器，其中主机CP /控制器可以适当地使用任何“选择的”存储器 通过简单地将“路径控制数据”传播到两个控制器和所选择的存储器单元中的存储器。