公开(公告)号：US20180039447A1

公开(公告)日：2018-02-08

申请号：US15473866

申请日：2017-03-30

申请人： SK hynix Inc.

发明人： Joo-Young LEE

IPC分类号： G06F3/06 ,  G06F11/10 ,  G06F12/0802

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0866 ,  G06F13/1668 ,  G06F2212/222 ,  G06F2212/313 ,  G06F2212/60 ,  G06F2212/7203

摘要： A memory system includes: a non-volatile memory device; a host controller suitable for generating a cache read command for controlling a cache read operation of the non-volatile memory device and at least one other command for controlling at least one other operation of the non-volatile memory device excluding the cache read operation in response to a request received from a host; and a memory controller suitable for controlling an operation of the non-volatile memory device in response to the cache read command and the at least one other command that are inputted from the host controller. The memory controller suitable for checking out the operation of the non-volatile memory device corresponding to a command that is inputted next to the input of the cache read command, and adding a read operation command including a read preparation command or a read end command next to the cache read command.

公开(公告)号：US20180004432A1

公开(公告)日：2018-01-04

申请号：US15633571

申请日：2017-06-26

申请人： Intel Corporation

发明人： Eric J. DAHLEN ,  Glenn J. HINTON ,  Raj K. RAMANUJAN

IPC分类号： G06F3/06 ,  G06F12/0893 ,  G06F12/0868 ,  G06F12/02 ,  G06F12/06 ,  G11C14/00 ,  G06F11/07

CPC分类号： G06F3/0611 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/0766 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0868 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C14/009

摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

公开(公告)号：US20170371795A1

公开(公告)日：2017-12-28

申请号：US15193952

申请日：2016-06-27

申请人： INTEL CORPORATION

发明人： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC分类号： G06F12/0873 ,  G06F12/123 ,  G06F12/0804

CPC分类号： G06F12/0873 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/124 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/608

摘要： An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.

公开(公告)号：US20170371792A1

公开(公告)日：2017-12-28

申请号：US15193001

申请日：2016-06-24

申请人： QUALCOMM Incorporated

发明人： Andres Alejandro OPORTUS VALENZUELA ,  Nieyan GENG ,  Christopher Edward KOOB ,  Gurvinder Singh CHHABRA ,  Richard SENIOR ,  Anand JANAKIRAMAN

IPC分类号： G06F12/0871 ,  G06F12/0868

CPC分类号： G06F12/0871 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/281 ,  G06F2212/282 ,  G06F2212/313 ,  G06F2212/401 ,  G06F2212/601 ,  G06F2212/608

摘要： In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time

公开(公告)号：US20170357590A1

公开(公告)日：2017-12-14

申请号：US15689767

申请日：2017-08-29

申请人： Silicon Motion, Inc.

发明人： Yang-Chih Shen ,  Che-Wei Hsu

IPC分类号： G06F12/0873

CPC分类号： G06F12/0873 ,  G06F2212/1021 ,  G06F2212/313 ,  G06F2212/608

摘要： The invention introduces a method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected.

公开(公告)号：US09842053B2

公开(公告)日：2017-12-12

申请号：US13837210

申请日：2013-03-15

申请人： SanDisk Technologies LLC

发明人： Vikram Joshi ,  Yang Luan ,  Michael F. Brown ,  Bhavesh Mehta

IPC分类号： G06F12/0868 ,  G06F12/0804 ,  G06F12/0871

CPC分类号： G06F12/0868 ,  G06F12/0804 ,  G06F12/0871 ,  G06F2212/313 ,  G06F2212/466

摘要： A cache log module stores an ordered log of cache storage operations sequentially within the physical address space of a non-volatile storage device. The log may be divided into segments, each comprising a set of log entries. Data admitted into the cache may be associated with respective log segments. Cache data may be associated with the log segment that corresponds to the cache storage operation in which the cache data was written into the cache. The backing store of the data may be synchronized to a particular log segment by identifying the cache data pertaining to the segment (using the associations), and writing the identified data to the backing store. Data lost from the cache may be recovered from the log by, inter alia, committing entries in the log after the last synchronization time of the backing store.

公开(公告)号：US20170308308A1

公开(公告)日：2017-10-26

申请号：US15136136

申请日：2016-04-22

申请人： International Business Machines Corporation

发明人： Kevin J. Ash ,  Matthew J. Kalos, II ,  Brian A. Rinaldi

IPC分类号： G06F3/06 ,  G06F12/128

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/313

摘要： A method for maintaining intelligent write ordering in an asynchronous data replication system is disclosed. In one embodiment, such a method includes performing the following, in order, for each extent of each rank of the primary storage device: (1) determining which primary volume the extent is associated with on the primary storage device; (2) if the primary volume that is associated with the extent is in a mirroring relationship with a corresponding secondary volume on the secondary storage device, scanning an out-of sync bitmap associated with the primary volume; and (3) sending, from the primary volume to the secondary volume, tracks in the extent having corresponding bits set in the out-of sync bitmap. A corresponding system and computer program product are also disclosed.

公开(公告)号：US20170293427A1

公开(公告)日：2017-10-12

申请号：US15247619

申请日：2016-08-25

申请人： SK hynix Inc.

发明人： Jung-Hyun KWON ,  Yong-Ju KIM ,  Sang-Gu JO ,  Jae-Sun LEE ,  Do-Sun HONG ,  Sung-Eun LEE ,  Jing-Zhe XU ,  Dong-Gun KIM

IPC分类号： G06F3/06 ,  G06F12/06

CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0638 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/205 ,  G06F2212/222 ,  G06F2212/2515 ,  G06F2212/313 ,  G06F2212/502

摘要： A memory module may include a first memory device configured to be controlled by a host memory controller, to transmit/receive data to/from the host memory controller in a first mode, and to transmit/receive data to/from a module memory controller in a second mode, a second memory device configured to be controlled by the module memory controller and to transmit/receive data to/from the module memory controller in the second mode, and the module memory controller configured to monitor control of the first memory device by the host memory controller, to exchange data such that the data is transmitted/received between the first memory device and the second memory device in the second mode, and to control the second memory device.

公开(公告)号：US09781226B2

公开(公告)日：2017-10-03

申请号：US15229297

申请日：2016-08-05

申请人： EMC Corporation

发明人： Philip Derbeko ,  Anat Eyal ,  Arieh Don ,  Zvi Gabriel Benhanokh ,  Alex Veprinsky

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  H04L29/08 ,  G06F12/0846 ,  H04L12/825 ,  H04L12/911 ,  H04L29/06 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897

CPC分类号： H04L67/2842 ,  G06F12/0804 ,  G06F12/0846 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/262 ,  G06F2212/283 ,  G06F2212/311 ,  G06F2212/313 ,  H04L47/25 ,  H04L47/822 ,  H04L67/1097 ,  H04L67/42

摘要： A method, computer program product, and computing system for processing one or more data chunks on a host server. The one or more data chunks are destined for storage within a portion of a data array coupled to the host server. The one or more data chunks are stored within a host cache system included within the host server. Storage criteria concerning the portion of a data array is reviewed. The storage criteria includes an array bandwidth allotment that defines a maximum bandwidth between the host server and the portion of the data array. The one or more data chunks are written to the portion of the data array based, at least in part, upon the storage criteria.

公开(公告)号：US09778850B1

公开(公告)日：2017-10-03

申请号：US14971112

申请日：2015-12-16

申请人： EMC Corporation

发明人： Gang Cao ,  Shay Harel ,  Walter Wang ,  Feng Zhang ,  Zhu Zhang

IPC分类号： G06F3/06

CPC分类号： G06F3/061 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7203

摘要： Described are techniques for processing a write operation that writes first data to a target location of a logical address range of a logical device. It is determined whether the target location is mapped to physical storage. Responsive to determining that the target location is not mapped to physical storage, performing first processing to service the write operation. The first processing includes sending the write operation along with a hint to a caching layer where the hint indicates to store zeroes to locations that do not include user data. The caching layer forms a data portion denoting data stored at a logical address subrange of the logical device. The logical address subrange includes the target location. The data portion includes the first data and zeroes stored at remaining locations of the logical address subrange not including user data. The data portion is stored in cache by the caching layer.