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公开(公告)号：US20180157427A1
公开(公告)日：2018-06-07
申请号：US15726460
申请日：2017-10-06
申请人： SK hynix Inc.
发明人： Do-Sun HONG , Yong-Ju KIM , Dong-Gun KIM
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0647 , G06F3/0652 , G06F3/0673 , G06F3/0679 , G06F12/0246 , G06F2212/1036 , G06F2212/1041 , G06F2212/7201 , G06F2212/7211
摘要： A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.
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公开(公告)号：US20170336985A1
公开(公告)日：2017-11-23
申请号：US15353844
申请日：2016-11-17
申请人： SK hynix Inc.
发明人： Dong-Gun KIM
CPC分类号： G06F3/0608 , G06F3/064 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A method for operating a memory system includes detecting a size of a data requested by a host, generating a first data that represents the size of the requested data and a second data that represents a remaining empty space other than a space for the requested data in a first region having a unit size of data storage in a memory device when the size of the requested data is smaller than the first region and the request is to write the requested data into the memory device, and storing the first data and the second data in the memory device along with the requested data.
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公开(公告)号：US20170293427A1
公开(公告)日：2017-10-12
申请号：US15247619
申请日：2016-08-25
申请人： SK hynix Inc.
发明人： Jung-Hyun KWON , Yong-Ju KIM , Sang-Gu JO , Jae-Sun LEE , Do-Sun HONG , Sung-Eun LEE , Jing-Zhe XU , Dong-Gun KIM
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0638 , G06F12/0868 , G06F2212/1016 , G06F2212/205 , G06F2212/222 , G06F2212/2515 , G06F2212/313 , G06F2212/502
摘要： A memory module may include a first memory device configured to be controlled by a host memory controller, to transmit/receive data to/from the host memory controller in a first mode, and to transmit/receive data to/from a module memory controller in a second mode, a second memory device configured to be controlled by the module memory controller and to transmit/receive data to/from the module memory controller in the second mode, and the module memory controller configured to monitor control of the first memory device by the host memory controller, to exchange data such that the data is transmitted/received between the first memory device and the second memory device in the second mode, and to control the second memory device.
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公开(公告)号：US20150052310A1
公开(公告)日：2015-02-19
申请号：US14333185
申请日：2014-07-16
申请人： SK hynix Inc.
发明人： Dong-Gun KIM , Yong-Kee KWON , Hong-Sik KIM
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0806 , G06F12/0897
摘要： A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.
摘要翻译： 高速缓存设备可以包括包括第一组和第一组对应的多个方式的第一高速缓存，以及包括与第二组对应的第二组和多个方式的第二高速缓存。 第二组与第一组相关，取决于第一组的方式的空缺。
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公开(公告)号：US20190163570A1
公开(公告)日：2019-05-30
申请号：US16203862
申请日：2018-11-29
申请人： SK hynix Inc.
发明人： Yong-Ju KIM , Do-Sun HONG , Dong-Gun KIM
CPC分类号： G06F11/1068 , G06F11/1004 , G06F11/1048 , G11C29/42 , G11C29/44 , G11C29/52 , G11C2029/0411 , G11C2029/4402 , H03M13/1515
摘要： A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.
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公开(公告)号：US20170371800A1
公开(公告)日：2017-12-28
申请号：US15598401
申请日：2017-05-18
申请人： SK hynix Inc.
发明人： Dong-Gun KIM , Yong-Ju KIM , Sang-Gu JO , Do-Sun HONG
CPC分类号： G06F12/10 , G06F3/0616 , G06F3/064 , G06F3/0673 , G06F12/0246 , G06F2212/1036 , G06F2212/657 , G06F2212/7211
摘要： Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.
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公开(公告)号：US20150347290A1
公开(公告)日：2015-12-03
申请号：US14523363
申请日：2014-10-24
申请人： SK hynix Inc.
发明人： Dong-Gun KIM , Yong-Kee KWON , Hong-Sik KIM
CPC分类号： G06F3/0688 , G06F3/0608 , G06F3/0616 , G06F3/0638 , G06F3/0644 , G06F3/0679
摘要： A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.
摘要翻译： 半导体器件可以包括第一存储器单元阵列，其被配置为在第一基础上存储根据第一地址的数据;第二存储单元阵列，被配置为根据第二地址在第二基础上存储数据，该第二地址相对小于第一基础 配置为在写入请求期间选择第一存储单元阵列和第二存储单元阵列之一以存储数据的存储器选择器，以及地址映射表，被配置为在第一和第二地址之间存储映射信息，以存储在第二存储单元阵列 存储单元阵列。
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公开(公告)号：US20150134876A1
公开(公告)日：2015-05-14
申请号：US14505042
申请日：2014-10-02
申请人： SK hynix Inc.
发明人： Dong-Gun KIM , Yong-Kee KWON , Hong-Sik KIM
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/0652 , G06F3/0688 , G06F12/0246 , G06F2212/1024 , G06F2212/7205 , G06F2212/7208
摘要： A data storage device may include: a data storage unit comprising a plurality of channels each having a plurality of nonvolatile memory devices; and a control unit configured to control a garbage collection operation of selecting a first block included in a first channel as a victim block and copying first data included in the first block into a second block included in a second channel that is selected.
摘要翻译： 数据存储装置可以包括：数据存储单元，包括多个通道，每个通道具有多个非易失性存储器件; 以及控制单元，被配置为控制选择包括在第一通道中的第一块的垃圾回收操作作为受害块，并将包括在第一块中的第一数据复制到包括在所选择的第二通道中的第二块中。
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公开(公告)号：US20180321878A1
公开(公告)日：2018-11-08
申请号：US15915147
申请日：2018-03-08
申请人： SK hynix Inc.
发明人： Do-Sun HONG , Dong-Gun KIM , Yong-Ju KIM
CPC分类号： G06F3/0659 , G06F3/0616 , G06F3/0644 , G06F3/0679 , G06F12/10 , G06F2212/1036 , G06F2212/202 , G06F2212/657
摘要： A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.
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公开(公告)号：US20180130526A1
公开(公告)日：2018-05-10
申请号：US15661087
申请日：2017-07-27
申请人： SK hynix Inc.
发明人： Do-Sun HONG , Yong-Ju KIM , Dong-Gun KIM
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0076
摘要： A method for refreshing memory cells includes: reading data from a plurality of memory cells; and performing a write operation with a first data onto memory cells from which the first data is read among the plurality of memory cells.
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