公开(公告)号：US20240045808A1

公开(公告)日：2024-02-08

申请号：US18490588

申请日：2023-10-19

申请人： Apple Inc.

发明人： Justin A. Hensley ,  Karl D. Mann ,  Yoong Chert Foo ,  Terence M. Potter ,  Frank W. Liljeros ,  Ralph C. Taylor

IPC分类号： G06F12/1018 ,  G06F12/084

CPC分类号： G06F12/1018 ,  G06F12/084 ,  G06F30/392

摘要： Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

公开(公告)号：US11893335B1

公开(公告)日：2024-02-06

申请号：US17477855

申请日：2021-09-17

申请人： Cadence Design Systems, Inc.

发明人： Arnold Jean Marie Gustave Ginetti

IPC分类号： G06F30/394 ,  G06F30/31 ,  G06F30/392 ,  G06F111/20

CPC分类号： G06F30/394 ,  G06F30/31 ,  G06F30/392 ,  G06F2111/20

摘要： Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving a selection of an instance associated with an electronic design at an electronic design schematic displayed on a graphical user interface. Embodiments may also include selecting a corresponding instance within an electronic design layout displayed on a graphical user interface. Embodiments may further include receiving a selection of a source topology and routing at the electronic design layout displayed on the graphical user interface, based upon at least in part, the source topology.

公开(公告)号：US20240037311A1

公开(公告)日：2024-02-01

申请号：US17814855

申请日：2022-07-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ralf Richter ,  Lukas Daellenbach

IPC分类号： G06F30/394 ,  G06F30/392

CPC分类号： G06F30/394 ,  G06F30/392 ,  G06F2111/04

摘要： A computer implemented method for a multi-layer integrated circuit routing tool connecting sources with nets to sinks in a hierarchical multi-layer integrated circuit design environment, the method including creating a cycle reach table containing a first set of information parameters for two dimensional nets per metal layer combination, creating a repeater reach table containing a second set of information parameters per constraint class, preparing a working list of nets, preparing a list of blocks larger than repeater reach dimensions, connecting a source pin to a sink pin on preassigned metal layers, by routing the net based on the given constraint class.

公开(公告)号：US20240030921A1

公开(公告)日：2024-01-25

申请号：US18482172

申请日：2023-10-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Ying HUANG ,  Changlin HUANG ,  Jing DING ,  Qingchao MENG

IPC分类号： H03K19/0185 ,  G06F30/392

CPC分类号： H03K19/018521 ,  G06F30/392 ,  G06F2119/06

摘要： A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.

公开(公告)号：US11881477B2

公开(公告)日：2024-01-23

申请号：US16902636

申请日：2020-06-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yung Feng Chang ,  Bao-Ru Young ,  Yu-Jung Chang ,  Tzung-Chi Lee ,  Tung-Heng Hsieh ,  Chun-Chia Hsu

IPC分类号： H01L27/08 ,  H01L27/02 ,  H01L23/52 ,  H01L29/66 ,  H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  G06F30/392 ,  G06F30/398 ,  G06F119/02 ,  G06F119/22

CPC分类号： H01L27/0207 ,  G06F30/392 ,  G06F30/398 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  G06F2119/02 ,  G06F2119/22

摘要： An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.

公开(公告)号：US11880743B2

公开(公告)日：2024-01-23

申请号：US18168138

申请日：2023-02-13

申请人： International Business Machines Corporation

发明人： Sergey Bravyi ,  Andrew W. Cross ,  Shelly-Erika Garion ,  Dmitri Maslov

IPC分类号： G06N10/00 ,  G06F30/327 ,  G06F30/392 ,  G06N10/20 ,  G06F111/02 ,  G06F119/02

CPC分类号： G06N10/00 ,  G06F30/327 ,  G06F30/392 ,  G06N10/20 ,  G06F2111/02 ,  G06F2119/02

摘要： Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.

公开(公告)号：US20240020454A1

公开(公告)日：2024-01-18

申请号：US18362957

申请日：2023-07-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng LIN ,  Hui-Ting YANG ,  Jiann-Tyng TZENG ,  Lipen YUAN ,  Wei-An LAI

IPC分类号： G06F30/392 ,  H01L27/02 ,  G06F30/398

CPC分类号： G06F30/392 ,  H01L27/0207 ,  G06F30/398

摘要： A method (of forming a semiconductor device) including forming cell regions (in alternating first and second rows having first and second heights) including forming a majority of the cell regions in the first rows including: limiting a height of the majority of the cell regions to be single-row cell regions that span corresponding single one of the first rows but do not extend therebeyond; and forming a minority of the cell regions correspondingly in at least the first rows including reducing widths of the multi-row cell regions to be smaller than comparable single-row cell regions; and expanding heights of the minority of the cell regions to be multi-row cell regions, each of the multi-row cell regions spanning a corresponding single first row and at least a corresponding second row such that cell region densities of the second rows are at least about forty percent.

公开(公告)号：US11876088B2

公开(公告)日：2024-01-16

申请号：US17527883

申请日：2021-11-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

发明人： Yang Zhou ,  Liu Han ,  Qingchao Meng ,  XinYong Wang ,  ZeJian Cai

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L25/065 ,  H01L23/48 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8238 ,  H01L25/00 ,  G06F30/392 ,  H01L21/74

CPC分类号： H01L27/0207 ,  G06F30/392 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76898 ,  H01L21/823892 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0928 ,  H01L2225/06513 ,  H01L2225/06541

摘要： An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.

公开(公告)号：US11868699B2

公开(公告)日：2024-01-09

申请号：US18065299

申请日：2022-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Pochun Wang ,  Yu-Jung Chang ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang

IPC分类号： G06F30/392 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20 ,  H01L23/522 ,  H01L23/528 ,  G06F30/39

CPC分类号： G06F30/392 ,  G06F30/39 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20

摘要： An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

公开(公告)号：US11861290B2

公开(公告)日：2024-01-02

申请号：US18048702

申请日：2022-10-21

申请人： X Development LLC

发明人： Brian Adolf ,  Patricia Prewitt

IPC分类号： G06F30/398 ,  G06F30/392 ,  H04J14/02

CPC分类号： G06F30/398 ,  G06F30/392 ,  H04J14/02

摘要： In some embodiments, logic stored on a computer-readable medium, in response to execution, causes a computing system to conduct an inverse design process to generate a plurality of segmented designs corresponding to a plurality of device specifications, determine at least one highly impactful design area based on the plurality of segmented designs; and designate the at least one highly impactful design area as a static design area. In some embodiments, a product line comprising a plurality of physical devices is provided. Each physical device of the plurality of physical devices includes a design region that includes a static design area and a customized design area. The static design area for each physical device is the same for each physical device of the plurality of physical devices, and the customized design area for each physical device is different for each physical device of the plurality of physical devices.