公开(公告)号：US09673821B1

公开(公告)日：2017-06-06

申请号：US14925164

申请日：2015-10-28

Applicant: Swaroop Ghosh ,  Kenneth Ramclam

Inventor： Swaroop Ghosh ,  Kenneth Ramclam

IPC: H03L5/00 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  G11C11/4087 ,  G11C11/4094 ,  H03K3/012 ,  H03K3/356113

Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

公开(公告)号：US09672890B2

公开(公告)日：2017-06-06

申请号：US14802178

申请日：2015-07-17

Applicant: SK hynix Inc.

Inventor： Jung Taek You

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408 ,  G11C7/08 ,  G11C11/4091 ,  G11C29/50

CPC classification number: G11C11/406 ,  G11C7/08 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C29/50016

Abstract: A semiconductor memory apparatus includes a plurality of cell arrays; and a use information storage block configured to determine whether a data write operation has already been performed for the plurality of cell arrays, and generate a plurality of control signals, wherein the semiconductor memory apparatus is configured to control a refresh operation for the plurality of cell arrays according to the plurality of control signals.

公开(公告)号：US20170125084A1

公开(公告)日：2017-05-04

申请号：US15403513

申请日：2017-01-11

Applicant: LONGITUDE SEMICONDUCTOR S.A.R.L.

Inventor： Chikara Kondo

IPC: G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.

公开(公告)号：US09640245B2

公开(公告)日：2017-05-02

申请号：US14798176

申请日：2015-07-13

Applicant: SK hynix Inc.

Inventor： Sun-Hye Shin ,  Nak-Kyu Park

IPC: G11C7/10 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/408 ,  G11C7/10 ,  G11C7/1027 ,  G11C7/1042 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/005

Abstract: A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.

公开(公告)号：US20170117033A1

公开(公告)日：2017-04-27

申请号：US15224683

申请日：2016-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-yeon Doo ,  Tae-young Oh ,  Cheol Kim ,  Geun-tae Park

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/40626 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091

Abstract: Provided is a method of refreshing a memory device by controlling a self-refresh cycle according to temperature. In the method, first self-refresh and second self-refresh are performed according to inner temperature of the memory device and a self-refresh cycle is controlled such that an all-bank-refresh (ABR) operation is not performed simultaneously with the start of the second self-refresh. The ABR operation is performed at the start of third self-refresh when the sum of a section of the first self-refresh in which the ABR operation is not performed and a section of the second self-refresh in which the ABR operation is not performed corresponds to a self-refresh cycle.

公开(公告)号：US09627095B1

公开(公告)日：2017-04-18

申请号：US15230122

申请日：2016-08-05

Applicant: SK hynix Inc.

Inventor： Jing-Zhe Xu ,  Yong-Ju Kim ,  Jung-Hyun Kwon ,  Sung-Eun Lee ,  Jae-Sun Lee

IPC: G11C29/00 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C17/16

CPC classification number: G11C29/76 ,  G06F12/0246 ,  G11C5/04 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C17/16 ,  G11C29/72 ,  G11C29/78 ,  G11C29/781 ,  G11C29/808 ,  G11C29/814 ,  G11C29/832 ,  G11C29/84 ,  G11C29/886

Abstract: A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.

公开(公告)号：US09620195B1

公开(公告)日：2017-04-11

申请号：US15236267

申请日：2016-08-12

Applicant: SK hynix Inc.

Inventor： Sang-Ah Hyun ,  Jeong-Tae Hwang

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4074 ,  G11C29/02 ,  G11C8/18 ,  G11C11/4076

CPC classification number: G11C11/40618 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C29/02 ,  G11C29/783 ,  G11C2211/4061

Abstract: A memory device may include a plurality of memory banks; a setting circuit capable of setting at least one of an advanced refresh mode and a piled refresh mode; and a refresh control unit capable of controlling the plurality of memory banks into a plurality of groups and for activating the plurality of groups to be refreshed at different times when a refresh command is applied, wherein the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups a first number of times, which is more than two and determined based on the additional setting information.

公开(公告)号：US09607682B1

公开(公告)日：2017-03-28

申请号：US15083077

申请日：2016-03-28

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G11C7/10 ,  G11C8/12 ,  G11C8/10

CPC classification number: G11C11/4087 ,  G06F12/06 ,  G06F2212/1041 ,  G11C7/1006 ,  G11C8/10 ,  G11C8/12

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

公开(公告)号：US09607677B2

公开(公告)日：2017-03-28

申请号：US14675149

申请日：2015-03-31

Applicant: Micron Technology, Inc.

Inventor： Takaaki Nakamura ,  Kazuya Saso

IPC: G11C7/00 ,  G11C8/00 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40622 ,  G11C11/4087

Abstract: An example apparatus includes an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes a plurality of counter cells configured to count through count values between a minimum count value to a maximum count value, wherein an output of each of the plurality of counter cells each corresponds to an address bit of the refresh address, and a reset circuit coupled to a counter cell of the plurality of counter cells, wherein the reset circuit is configured to reset the counter cell of the plurality of counter cells to an initial value responsive to the plurality of counter cells changing from a first count value to a second count value to skip at least some of the count values to provide the refresh addresses, wherein the first and second count values are less than the maximum count value.

公开(公告)号：US20170069369A1

公开(公告)日：2017-03-09

申请号：US15207989

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  H01L27/108 ,  H01L25/065

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

Abstract translation: 半导体存储器件包括具有用于管芯端接的第一终端电阻器和第二存储器管芯的第一存储器管芯，具有用于管芯端接的第二终端电阻器并形成在第一存储器管芯上。 第一和第二存储器管芯中的每一个具有中心焊盘类型并且基于多级结构进行操作。 当访问第一存储器管芯时，第二终端电阻器连接到第二存储管芯，并且当访问第二存储器管芯时，第一终端电阻器连接到第一存储器管芯。