公开(公告)号：US20150200089A1

公开(公告)日：2015-07-16

申请号：US14152497

申请日：2014-01-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shich-Chang SUEN ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC分类号： H01L21/02 ,  H01L21/28

CPC分类号： H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

摘要翻译： 本公开提供了一种用于形成集成电路（IC）结构的方法。 该方法包括提供金属栅极（MG），形成在MG上的蚀刻停止层（ESL）以及形成在ESL上的电介质层。 该方法还包括蚀刻ESL和介电层以形成沟槽。 暴露在沟槽中的MG的表面被氧化以在MG上形成第一氧化物层。 该方法还包括使用H 3 PO 4溶液去除第一氧化物层。

公开(公告)号：US08946078B2

公开(公告)日：2015-02-03

申请号：US13426624

申请日：2012-03-22

申请人： Tong-Yu Chen ,  Chih-Jung Wang

发明人： Tong-Yu Chen ,  Chih-Jung Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/66795

摘要： The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

摘要翻译： 本发明提供一种在半导体衬底中形成沟槽的方法。 首先，在半导体衬底上形成第一图案化掩模层。 第一图案化掩模层具有第一沟槽。 然后，沿着第一沟槽形成材料层。 然后，在材料层上形成第二图案化掩模层以完全填充第一沟槽。 当保持第二图案化掩模层和半导体衬底之间的材料层的部分以形成第二沟槽时，去除材料层的一部分。 最后，通过使用第一图案化掩模层和第二图案化掩模层作为掩模来执行蚀刻工艺。

公开(公告)号：US20140199827A1

公开(公告)日：2014-07-17

申请号：US14225632

申请日：2014-03-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya Hui Chang

IPC分类号： H01L21/28

CPC分类号： H01L21/76816 ,  H01L21/28132 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/105

摘要： A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.

摘要翻译： 公开了一种用于小沟槽图案化的半导体器件和方法。 该器件包括多个栅极结构和侧壁间隔物，以及设置在侧壁间隔物上的蚀刻缓冲层。 蚀刻缓冲层包括设置在侧壁间隔物的上部上的突出部分，其侧向延伸。 相邻突出部件的边缘之间的宽度比相邻侧壁间隔件之间的宽度窄。

公开(公告)号：US20140159169A1

公开(公告)日：2014-06-12

申请号：US14181304

申请日：2014-02-14

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Ruilong XIE ,  David V. HORAK ,  Su Chen FAN ,  Pranatharthiharan Haran BALASUBRAMANIAN

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/28132 ,  H01L21/28247 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66553

摘要： A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.

摘要翻译： 公开了一种用于凹陷和封盖金属栅极结构的方法。 实施例包括：在基板上形成虚拟栅电极; 在虚拟栅电极上形成硬掩模; 在虚拟栅电极和硬掩模的相对侧上形成间隔物; 在邻近所述间隔物的衬底上形成层间电介质（ILD）; 在所述ILD中形成第一沟槽至所述伪栅电极; 去除所述伪栅电极以在所述第一沟槽下方形成第二沟槽; 在所述第一和第二沟槽中形成金属栅极结构; 以及在所述金属栅极结构上形成栅极盖。

公开(公告)号：US20140017889A1

公开(公告)日：2014-01-16

申请号：US13679518

申请日：2012-11-16

申请人： SK HYNIX INC.

发明人： Ki Lyoung LEE ,  Cheol Kyu BOK ,  Won Kyu KIM

IPC分类号： H01L21/48

CPC分类号： H01L21/4846 ,  H01L21/28132 ,  H01L21/3086 ,  H01L27/11531 ,  H01L2924/0002

摘要： A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.

摘要翻译： 提供了一种使用双SPT工艺形成半导体器件的精细图案的方法，其能够通过应用包括负SPT处理的双重SPT处理来实现具有均匀细线宽度的线和间隔图案。 该方法包括第一SPT处理和第二SPT处理，第二SPT处理包括负SPT处理。

公开(公告)号：US20130328111A1

公开(公告)日：2013-12-12

申请号：US13491857

申请日：2012-06-08

申请人： Ruilong Xie ,  David V. Horak ,  Su Chen Fan ,  Pranatharthiharan Haran Balasubramanian

发明人： Ruilong Xie ,  David V. Horak ,  Su Chen Fan ,  Pranatharthiharan Haran Balasubramanian

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/28132 ,  H01L21/28247 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66553

摘要： A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.

摘要翻译： 公开了一种用于凹陷和封盖金属栅极结构的方法。 实施例包括：在基板上形成虚拟栅电极; 在虚拟栅电极上形成硬掩模; 在虚拟栅电极和硬掩模的相对侧上形成间隔物; 在邻近所述间隔物的衬底上形成层间电介质（ILD）; 在所述ILD中形成第一沟槽至所述伪栅电极; 去除所述伪栅电极以在所述第一沟槽下方形成第二沟槽; 在所述第一和第二沟槽中形成金属栅极结构; 以及在所述金属栅极结构上形成栅极盖。

公开(公告)号：US08592265B2

公开(公告)日：2013-11-26

申请号：US13242382

申请日：2011-09-23

申请人： Dong-Kwon Kim ,  Young-Ju Park ,  Dong-Hyuk Yeam ,  Yoo-Jung Lee ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Heung-Sik Park

发明人： Dong-Kwon Kim ,  Young-Ju Park ,  Dong-Hyuk Yeam ,  Yoo-Jung Lee ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Heung-Sik Park

IPC分类号： H01L21/338

CPC分类号： H01L21/28132 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

摘要： Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.

摘要翻译： 示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。 该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚设栅电极的一部分形成第一凹槽， 所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部 第二个凹槽

公开(公告)号：US20130175637A1

公开(公告)日：2013-07-11

申请号：US13343818

申请日：2012-01-05

申请人： Ya Hui Chang

发明人： Ya Hui Chang

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/76816 ,  H01L21/28132 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/105

摘要： A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.

摘要翻译： 公开了一种用于小沟槽图案化的半导体器件和方法。 该器件包括多个栅极结构和侧壁间隔物，以及设置在侧壁间隔物上的蚀刻缓冲层。 蚀刻缓冲层包括设置在侧壁间隔物的上部上的突出部分，其侧向延伸。 相邻突出部件的边缘之间的宽度比相邻侧壁间隔件之间的宽度窄。

公开(公告)号：US08409787B2

公开(公告)日：2013-04-02

申请号：US13041696

申请日：2011-03-07

申请人： Choong-Ryul Ryou ,  Hee-Sung Kang

发明人： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC分类号： H01L21/00 ,  H01L21/76

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

摘要： A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

公开(公告)号：US20130001663A1

公开(公告)日：2013-01-03

申请号：US13608190

申请日：2012-09-10

申请人： Todd R. Abbott ,  Homer M. Manning

发明人： Todd R. Abbott ,  Homer M. Manning

IPC分类号： H01L27/108

CPC分类号： H01L27/10885 ,  H01L21/28132 ,  H01L27/10808 ,  H01L27/10876 ,  Y10S257/908

摘要： DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

摘要翻译： 具有约4F2的单元面积的DRAM单元阵列包括具有掩埋位线和垂直双栅电极的垂直晶体管阵列。 掩埋位线包括硅化物材料并且被设置在衬底的表面下方。 字线可选地由硅化物材料形成并形成垂直晶体管的栅电极。 垂直晶体管可以包括顺序形成的掺杂多晶硅层或掺杂的外延层。 至少一个掩埋位线与垂直晶体管的至少一个垂直栅电极正交。