公开(公告)号：US20080238754A1

公开(公告)日：2008-10-02

申请号：US11690952

申请日：2007-03-26

Applicant: Niels Knudsen

Inventor： Niels Knudsen

IPC: H03M1/50

CPC classification number: H03M1/124 ,  H03M1/167

Abstract: A Sampled Pipeline Subranging Converter (SPSC) may include at least one stage—e.g. at least the input stage—operating in a time-continuous fashion. In the time continuous input stage, the analog input may be processed in two parallel paths. A lower path may comprise a track-and-hold (T/H) element, an Analog-to-Digital-Converter (ADC) and a Digital-to-Analog-Converter (DAC). The T/H element may be optional and may be present if required by the ADC. The signal entering the lower path may be sampled at the desired conversion rate. The time continuous stage(s) may additionally be configured with an upper path that includes a delay element configured to receive the analog input, a Low-Pass (LP) filter coupled to the delay element, and an anti alias filter. The output generated by the DAC may be subtracted from the output of the LP filter, and the resulting difference signal may be provided to the anti alias filter, which in turn may generate the residue (or error) output. The digital output of the time continuous converter may be calculated by combining the digital outputs of the various sections.

Abstract translation: 采样管线子转换器（SPSC）可以包括至少一个级 - 例如， 至少输入级 - 以时间连续的方式操作。 在时间连续输入级中，模拟输入可以以两个并行的路径进行处理。 较低路径可以包括跟踪保持（T / H）元件，模数转换器（ADC）和数模转换器（DAC）。 T / H元件可以是可选的，如果ADC需要，可以存在T / H元件。 可以以期望的转换速率对进入较低路径的信号进行采样。 时间连续级还可以被配置为具有被配置为接收模拟输入的延迟元件，耦合到延迟元件的低通滤波器（LP）滤波器）和反混叠滤波器的上路径。 可以从LP滤波器的输出中减去由DAC产生的输出，并将得到的差分信号提供给反混淆滤波器，反滤波器又可以产生残差（或误差）输出。 可以通过组合各部分的数字输出来计算时间连续变换器的数字输出。

公开(公告)号：US07336213B2

公开(公告)日：2008-02-26

申请号：US11305328

申请日：2005-12-16

Applicant: Nikhil Gupta ,  Alok K. Mittal

Inventor： Nikhil Gupta ,  Alok K. Mittal

IPC: H03M1/50

CPC classification number: H03M1/52

Abstract: Polarity independent precision measurement of an input voltage signal is accomplished using a voltage integrating circuit that receives a first positive reference voltage and the input voltage signal, wherein the first positive reference voltage is greater in magnitude than the input voltage signal. A resetting circuit is coupled to the voltage integrating circuit for stabilizing its output. A pair of comparators, each connected to the output of the voltage integrating circuit, make voltage comparisons against a second reference voltage and a third reference voltage respectively, wherein the second and third reference voltages are greater in magnitude than the first reference voltage. A time interval measurement circuit receives the outputs of the pair of comparators, and operates to measure the time taken for the output of the voltage integrating circuit to transit to the second reference voltage level and the third reference voltage level. The time interval measurement circuit provides an output for controlling the resetting circuit.

Abstract translation: 使用接收第一正参考电压和输入电压信号的电压积分电路来实现输入电压信号的极性独立精密测量，其中第一正参考电压的幅度大于输入电压信号。 复位电路耦合到电压积分电路以稳定其输出。 一对比较器分别连接到电压积分电路的输出端，分别对第二参考电压和第三参考电压进行电压比较，其中第二和第三参考电压的幅度大于第一参考电压。 时间间隔测量电路接收一对比较器的输出，并且操作以测量电压积分电路的输出转移到第二参考电压电平和第三参考电压电平所花费的时间。 时间间隔测量电路提供用于控制复位电路的输出。

公开(公告)号：US06970503B1

公开(公告)日：2005-11-29

申请号：US09556607

申请日：2000-04-21

Applicant: Arthur Joseph Kalb

Inventor： Arthur Joseph Kalb

IPC: H03K7/08 ,  H03M1/50 ,  H03M3/02 ,  H04L25/49

CPC classification number: H04L25/4902 ,  H03M3/412 ,  H03M3/424 ,  H03M3/432 ,  H03M3/454

Abstract: A circuit for converting an analog signal to a discrete pulse-width-modulated (PWM) signal uses a delta-sigma amplifier and a discrete PWM stage to produce a discrete PWM output signal having lower in-band signal noise then a PDM system and a lower signal distortion then a continuous PWM system. A multiple bit quantization stage drives the discrete PWM stage.

Abstract translation: 用于将模拟信号转换为离散脉宽调制（PWM）信号的电路使用Δ-Σ放大器和离散PWM级来产生具有较低带内信号噪声的离散PWM输出信号，然后PDM系统和 较低的信号失真，然后连续的PWM系统。 多位量化级驱动离散PWM级。

公开(公告)号：US20050134352A1

公开(公告)日：2005-06-23

申请号：US11002684

申请日：2004-12-03

Applicant: Makoto Yokoyama ,  Hajime Washio ,  Yuhichiroh Murakami ,  Kenji Hyoudou ,  Hiroshi Murofushi

Inventor： Makoto Yokoyama ,  Hajime Washio ,  Yuhichiroh Murakami ,  Kenji Hyoudou ,  Hiroshi Murofushi

IPC: G09G3/36 ,  G02F1/133 ,  G09G3/20 ,  H03K5/15 ,  H03M1/50

CPC classification number: G09G3/3688 ,  G09G2310/0289 ,  G09G2310/0294

Abstract: An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.

Abstract translation: 触发器的输出脉冲在提供给电平移位器的输入端子之前在延迟逆变器电路中被延迟。 然后，下一级触发器的输出脉冲被提供给第一触发器的复位端，并且还提供给电平移位器的使能端。 此外，电平移位器输出采样脉冲，其开始端等于提供给输入端子的脉冲的起始端和等于提供给使能端的脉冲的开始和脉冲。 通过这种布置，本发明提供了一种脉冲输出电路，一种使用脉冲输出电路的显示装置的驱动电路，一种显示装置和一种脉冲输出方法，该方法减少脉冲终端的延迟，从而顺序地从 多个输出端子。

公开(公告)号：US20050093724A1

公开(公告)日：2005-05-05

申请号：US10968671

申请日：2004-10-19

Applicant: Bengt Berg

Inventor： Bengt Berg

IPC: H03L7/06 ,  H01L20060101 ,  H03F1/26 ,  H03F1/30 ,  H03F3/213 ,  H03J3/06 ,  H03K3/00 ,  H03K5/08 ,  H03M1/00 ,  H03M1/08 ,  H03M1/50 ,  H04B1/04

CPC classification number: H03M1/0872 ,  H03K5/08 ,  H03M1/50

Abstract: An arrangement and a method in an integrated circuit for tuning and setting a value comprising a comparator circuit having a reference voltage input and a variable voltage input is provided to produce a digital value on an output depending on a comparison between the reference voltage and the variable voltage. A first clocked counter circuit is connected to the comparator to increase or decrease the value of the first clocked counter depending on the digital value supplied from the comparator. The arrangement further comprises a second clocked counter circuit connected to the comparator to increase the value of the second clocked counter for each change of value of the comparator, and a locking circuit connected to the second clocked counter circuit to lock the value stored in the first clocked counter circuit from further changes when the second clocked counter reaches a first threshold value.

Abstract translation: 提供了用于调谐和设置包括具有参考电压输入和可变电压输入的比较器电路的值的集成电路中的布置和方法，以根据参考电压和变量之间的比较在输出上产生数字值 电压。 第一时钟计数器电路连接到比较器，以根据从比较器提供的数字值增加或减小第一计时计数器的值。 该装置还包括连接到比较器的第二计时计数器电路，用于增加比较器的值的每个变化的第二时钟计数器的值，以及连接到第二时钟计数器电路的锁定电路，以锁定存储在第一 当第二时钟计数器达到第一阈值时，计时计数器电路进一步改变。

公开(公告)号：US06850178B2

公开(公告)日：2005-02-01

申请号：US10192605

申请日：2002-07-10

Applicant: Takamoto Watanabe

Inventor： Takamoto Watanabe

IPC: H03M1/14 ,  H03M1/06 ,  H03M1/50 ,  H03M1/60 ,  H03M1/12

CPC classification number: H03M1/0619 ,  G04F10/005 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

Abstract: An analog-to-digital conversion device is provided that uses pulse delay circuits to convert an input voltage into numerical data and offers a high resolution in analog-to-digital conversion or a high analog-to-digital conversion rate. The analog-to-digital conversion device includes an analog-to-digital conversion unit having a pulse delay circuit composed of a plurality of delay units. The delay units are driven with a voltage produced by amplifying or shifting an input voltage. The number of delay units through which a pulse signal has passed during a predetermined sampling cycle is adopted as a digitized value of the input voltage. Herein, delay units constituting another pulse delay circuit are driven with a voltage produced by inversely amplifying or shifting the input voltage. Every time the number of delay units through which a pulse signal has passed within the pulse delay circuit reaches a predetermined value determined with a set value, a sampling signal is transferred to the analog-to-digital conversion unit.

Abstract translation: 提供了一种使用脉冲延迟电路将输入电压转换为数字数据并在模数转换中提供高分辨率或高模数转换速率的模数转换装置。 模数转换装置包括具有由多个延迟单元组成的脉冲延迟电路的模数转换单元。 延迟单元由放大或移位输入电压产生的电压驱动。 作为输入电压的数字化值，采用脉冲信号在预定采样周期内通过的延迟单元的数量。 这里，构成另一个脉冲延迟电路的延迟单元由通过反相放大或移位输入电压而产生的电压驱动。 每当在脉冲延迟电路内通过脉冲信号的延迟单元的数量达到以设定值确定的预定值时，采样信号被传送到模拟 - 数字转换单元。

公开(公告)号：US6157672A

公开(公告)日：2000-12-05

申请号：US18837

申请日：1998-02-04

Applicant: Atsushi Iwata ,  Makoto Nagata

Inventor： Atsushi Iwata ,  Makoto Nagata

IPC: G06G7/161 ,  H03M1/50 ,  H03K7/08 ,  H03K9/08 ,  G06G7/12

CPC classification number: H03M1/504 ,  H03M1/502

Abstract: A pulse modulation operation circuit includes a current bus, a plurality of switch current sources connected parallel to each other and commonly connected to the current bus for generating current pulses corresponding to external input signals, charge conversion element connected to the current bus for integrating the current pulses and converting them into a charge, and an output for converting the charge into a binary digital signal and outputting the binary digital signal. Each pulse width modulation signal is input to a corresponding one of the switch current sources, which in turn generates a constant current for a period corresponding to the width of each pulse of the signal, to convert each signal pulse into a current pulse. The thus-obtained current pulses are added on the common current bus, thereby obtaining, by capacitive integration, a total charge Q.sub.total proportional to the sum of the widths of the current pulses. To this end, a reference charge counter circuit has a function for integration and a function for digitizing the total charge Q.sub.total in units of a reference charge Q.sub.std in real time.

Abstract translation: 脉冲调制运算电路包括电流总线，多个彼此并联连接的开关电流源，并且共同连接到当前总线，用于产生对应于外部输入信号的电流脉冲;电荷转换元件连接到当前总线，用于对电流进行积分 脉冲并将其转换成电荷，以及用于将电荷转换成二进制数字信号并输出​​二进制数字信号的输出。 每个脉冲宽度调制信号被输入到相应的一个开关电流源，开关电流源又产生恒定电流一段与信号的每个脉冲宽度相对应的电流，以将每个信号脉冲转换成电流脉冲。 这样获得的电流脉冲被加在公共电流总线上，从而通过电容积分获得与电流脉冲宽度之和成比例的总电荷Qtotal。 为此，参考电荷计数器电路具有用于积分的功能和用于以基准电荷Qstd为单位实时地数字化总电荷Qtotal的功能。

公开(公告)号：US5838754A

公开(公告)日：1998-11-17

申请号：US814835

申请日：1997-03-11

Applicant: Mark S. Gorbics ,  Keith M. Roberts ,  Richard L. Sumner

Inventor： Mark S. Gorbics ,  Keith M. Roberts ,  Richard L. Sumner

IPC: G04F10/06 ,  H03K5/159 ,  H03M1/06 ,  H03M1/50 ,  G06M3/00

CPC classification number: H03M1/0697 ,  G04F10/06 ,  H03K5/159 ,  H03M1/50 ,  H03M1/502

Abstract: A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.

Abstract translation: 游标延迟线内插器通过延迟具有等间隔抽头的延迟线中的周期性脉冲信号和大于脉冲周期1的谐波H的总延迟来提供小于时钟周期的精度电平。 延迟线的抽头被锁存和解码，以导出已经过去的脉冲周期的分数。 当内插器与粗计数器组合时，通过使粗计数器计数周期性脉冲信号的两个边缘以便在计数器和内插器之间提供冗余位来防止它们的输出之间的对准。 如果冗余位不相等，则在与内插器的输出组合之前校正计数器输出。

公开(公告)号：US5835552A

公开(公告)日：1998-11-10

申请号：US747129

申请日：1996-11-12

Applicant: Keiichi Kusumoto ,  Shiro Dosho ,  Yutaka Terada ,  Akira Matsuzawa

Inventor： Keiichi Kusumoto ,  Shiro Dosho ,  Yutaka Terada ,  Akira Matsuzawa

IPC: G01R29/027 ,  H03D3/04 ,  H03K9/06 ,  H03M1/50 ,  G01B7/00

CPC classification number: G04F10/005 ,  G01R29/027 ,  H03D3/04 ,  H03K9/06

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.

公开(公告)号：US5783957A

公开(公告)日：1998-07-21

申请号：US753917

申请日：1996-12-03

Applicant: Tadaaki Yamauchi

Inventor： Tadaaki Yamauchi

IPC: H03M1/12 ,  G11C7/06 ,  G11C11/409 ,  H03F3/45 ,  H03K5/02 ,  H03K17/687 ,  H03M1/50

CPC classification number: H03K5/023 ,  G11C7/062 ,  G11C7/065 ,  H03M1/504

Abstract: There is disclosed a differential amplifier circuit wherein resistors (89, 91) and capacitors (90, 92) are connected respectively between sources of a differential pair of NMOS transistors (85, 87) and a power supply (2). The resistors (89, 91) raise the source potential of the NMOS transistors to reduce current flows during the time no transition of signal level outputted from the differential amplifier circuit occurs, reducing power consumption in the differential amplifier circuit. The capacitor (90, 92) alleviate the effects of voltage drop by the resistors (89, 91) during the signal level transition to prevent reduction in operating speed of the differential amplifier circuit.