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    Methods of etching intermediate silicon germanium layers using ion implantation to promote selectivity
    101.
    发明申请
    Methods of etching intermediate silicon germanium layers using ion implantation to promote selectivity 有权
    使用离子注入蚀刻中间硅锗层以提高选择性的方法

    公开(公告)号：US20050003628A1

    公开(公告)日：2005-01-06

    申请号：US10884749

    申请日：2004-07-02

    申请人： Eun-jung Yun ,  Sung-young Lee ,  Chang-sub Lee ,  Sung-min Kim ,  Dong-gun Park

    发明人： Eun-jung Yun ,  Sung-young Lee ,  Chang-sub Lee ,  Sung-min Kim ,  Dong-gun Park

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/306 ,  H01L21/76

    CPC分类号： H01L21/30604

    摘要： An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into a portion of the intermediate SiGex layer exposed through the window in the implant mask and blocking implantation of ions into portions of the intermediate SiGex layer outside the window. The portions of the intermediate SiGex layer outside the window are etched and the portion of the intermediate SiGex layer exposed through the window having ions implanted therein is not substantially etched to form a patterned intermediate SiGex layer.

    摘要翻译： 通过在包括上下Si层和中间SiGex层的结构上形成具有窗口的注入掩模，可以形成集成电路器件结构。 离子通过上部Si层进入植入掩模中通过窗口暴露的中间SiGex层的一部分，并将离子注入到窗口外部的中间SiGex层的部分中。 蚀刻窗口外部的中间SiGex层的部分，并且通过其中注入离子的窗口露出的中间SiGex层的部分基本上不被蚀刻以形成图案化的中间SiGex层。

    Nonvolatile memory devices having gate structures doped by nitrogen
    102.
    发明授权
    Nonvolatile memory devices having gate structures doped by nitrogen 有权
    具有由氮掺杂的栅极结构的非易失性存储器件

    公开(公告)号：US08552488B2

    公开(公告)日：2013-10-08

    申请号：US13181134

    申请日：2011-07-12

    申请人： Chang-Hyun Lee ,  Dong-Gun Park

    发明人： Chang-Hyun Lee ,  Dong-Gun Park

    IPC分类号： H01L29/788

    CPC分类号： H01L21/265 ,  B82Y10/00 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/792

    摘要： Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

    摘要翻译： 在集成电路基板上提供集成电路基板和电荷存储图案的非易失性存储器件。 电荷存储图案具有侧壁，并且在电荷存储图案和集成电路基板之间设置隧道绝缘层。 在电荷存储图案上提供栅极图案。 在电荷存储图案和栅极图案之间设置隔离绝缘层。 电荷存储图案的侧壁包括第一氮掺杂层。 本文还提供了制造非易失性存储器件的相关方法。

    Semiconductor Devices Having Recessed Channels
    104.
    发明申请
    Semiconductor Devices Having Recessed Channels 失效
    具有嵌入式通道的半导体器件

    公开(公告)号：US20120305997A1

    公开(公告)日：2012-12-06

    申请号：US13586593

    申请日：2012-08-15

    申请人： Joo-Young Lee ,  Dong-Gun Park

    发明人： Joo-Young Lee ,  Dong-Gun Park

    IPC分类号： H01L29/78 ,  H01L27/088

    CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10876

    摘要： A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided.

    摘要翻译： 半导体器件包括衬底，栅极绝缘层，栅极结构，栅极间隔物以及第一和第二杂质区域。 衬底具有由隔离层限定的有源区。 有源区在其上具有栅极沟槽。 栅极绝缘层形成在栅极沟槽的内壁上。 栅极结构形成在栅极绝缘层上以填充栅极沟槽。 栅极结构的宽度小于栅极沟槽的宽度，并且在其第一部分处具有凹部。 栅极间隔件形成在栅极结构的侧壁上。 第一和第二杂质区域形成在与栅极结构相邻的有源区的上部。 第一杂质区比第二杂质区更靠近凹部。 还提供了相关方法。

    Semiconductor memory device having vertical channel transistor and method for fabricating the same
    105.
    发明授权
    Semiconductor memory device having vertical channel transistor and method for fabricating the same 有权
    具有垂直沟道晶体管的半导体存储器件及其制造方法

    公开(公告)号：US08283714B2

    公开(公告)日：2012-10-09

    申请号：US13085898

    申请日：2011-04-13

    申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

    发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

    摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions
    107.
    发明申请
    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions 审中-公开
    金属氧化物半导体场效应晶体管（MOSFET）包括嵌入式通道区域

    公开(公告)号：US20110079831A1

    公开(公告)日：2011-04-07

    申请号：US12966362

    申请日：2010-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

    IPC分类号： H01L29/772

    CPC分类号： H01L29/66583 ,  H01L29/1037 ,  H01L29/66651

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池在集成电路基板上具有集成电路基板和MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 在源区和漏区之间提供沟道区。 沟道区具有比源区和漏区的底表面低的凹陷区域。 还提供了制造晶体管的相关方法。

    Semiconductor devices including channel and junction regions of different semiconductor materials
    109.
    发明授权
    Semiconductor devices including channel and junction regions of different semiconductor materials 有权
    半导体器件包括不同半导体材料的沟道和结区

    公开(公告)号：US07859064B1

    公开(公告)日：2010-12-28

    申请号：US11849577

    申请日：2007-09-04

    申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/41

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

    METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES
    110.
    发明申请
    METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES 有权
    制造垂直通道半导体器件的方法

    公开(公告)号：US20100285645A1

    公开(公告)日：2010-11-11

    申请号：US12838826

    申请日：2010-07-19

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

    摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

    摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。